Hitachi AP1 - Page 75

LRA,LRB [
Instruction
LAR. LBR [
Instruction
-
-
----
One Instruction
Cycle
--
Rn Output
Instruction
Rn
Pattern Instruction
R2,R3
HMCS45C, HMCS45CL
(second cycle)
Rn Input
~
Instruction
Rn Sampling Clock
Figure 13 4-bit Data I/O Timing
Set Signal by the reset function
Set Instruction
Reset Instruction ___ --I
On
SED, REO.SEDO. [
REDO Instruction
TO (
Instruction
-
Latch
Figure 14 1-bit Discrete I/O Block Diagram
One Instruction Cycle
..,....----....
I~~t~u~/;~~set
On (LSI Din X
On Test
I--
Instruction It. ~
On Sampling
Clock
Figure 15 1·bit Discrete I/O Timing
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