Hitachi L32S02A User Manual

Use Rising Edge of WR# to latch data
MPU in A/D Separate ModeGPIO0
Use Falling Edge of WR# to latch data
1(HIGH)
GPIO1
Pin No.
MPU in A/D Multiplix Mode
0(LOW)Pin Name
I2C Slave Address is fixed to 0x7e/0x7f
CX_SDA CX_SCL
CX_PWM0 CX_SDA
CX_PWM0
CX_GPIO0 CX_GPIO1 DP_DE_FLD
uP_AD1 uP_AD7 uP_A0 uP_A2 uP_A5 uP_A3 uP_A4 uP_AD2 uP_AD5 uP_AD3 uP_A7 uP_A6 uP_AD4 uP_AD0 uP_AD6 uP_A1
8051_A6 8051_AD6 8051_AD4 8051_AD5 8051_AD3
CX_SCL
8051_AD7 8051_AD1 8051_A0 8051_A1 8051_A5 8051_A4 8051_A2 8051_A7 8051_AD0 8051_A3 8051_AD2
DP_HS DP_VS DP_CLK
DP8 DP16 DP10 DP14 DP13 DP4 DP6 DP9 DP7 DP18 DP17 DP23 DP3 DP19 DP11 DP12 DP1 DP0 DP2 DP15 DP20 DP22 DP5 DP21
3V_SDA 3V_SCL 5V_SDA 5V_SCL
8051_RD#
uP_A[0..7]
8051_WR#
uP_AD[0..7]
8051_ALE BRT_CNTL
8051_CS2CX
CX_INT#
RESET_H
DP_HS DP_VS DP_CLK
DP_DE_FLD
DP[0..23]
CX_VD33
5V_SB
RN3 100x4
1 2 3 4
8 7 6 5
R8 0
R14 0 R9 0 R11 0 R17 0
R19 10
C34
68pF_DNS
R15 0
R21 10_DNS
(2/4)
CPU INTERFACE
SVP-CX32_208 DIGITAL OUT
U1B SVP_CX32
55 61 60 56 57 58 62 63
83 82 81 80 79 78 77 76
84 86 85 59
64 65 66 67 68 69 70 71 37 36 35 34 33 32 31 30 29 26 25 24 22 21 18 17 16 15 14 11 10 9 8 7
4 5
23
6
PWM0 CS GPIO0 INTN SCL SDA WR# RD#
A_D0 A_D1 A_D2 A_D3 A_D4 A_D5 A_D6 A_D7
ALE RESET V5SF GPIO1
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7
DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 DP8 DP9
DP10 DP11 DP12 DP13 DP14 DP15 DP16 DP17 DP18 DP19 DP20 DP21 DP22 DP23
DP_HS DP_VS DP_CLK DP_DE_FLD
C35 0.1uF
C33 68pF_DNS
R10 0
RN2 100x4
1 2 3 4
8 7 6 5
C31 0.01uF
RN1 100x4
1 2 3 4
8 7 6 5
R20 10_DNS R16 10
R12
4.7K_DNS
RN4 100x4
1 2 3 4
8 7 6 5
R13 4.7K_DNS
5 5
4 4
3 3
2 2
1 1
DD CC BB AA
-12-
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Hitachi L32S02A Specifications

General

Brand	Hitachi
Model	L32S02A
Category	LCD TV
Language	English