e-ICE User’s Guide
16
Figure 20 Debug Option
Halt Instruction
The Halt instruction cannot be located at the last address (0x1fff) of Program Memory
ROM Bank0.
If a WDT overflow occurs during a Halt condition, it is possible that an erroneous stack
overflow may occur.
Pressing Stop during a Halt condition may result in incorrect PC values.
The first instruction after waking up from a Halt condition may execute correctly. To
resolve this issue add a NOP instruction to avoid this problem.
Executing a HALT instruction using Single Step may cause an immediate wake up.
Configuration Option IO/RES Setting
When the “PXn/RES Pin Option in the Configuration Options is set as an I/O PIN, the I/O
Reset, Poweron Reset, and Stop will all be invalid.
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