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HP 1630D User Manual

HP 1630D
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Model1630A/D/G
General
Information
Measurement
Configurations
Measurement
Functions
Memory
Data
Acquisition
:
1024
words
.
Table
1-1
.
Specifications
Note
:
Number
of
timing
channels
halved
in
Glitch
mode
.
Compare
:
16
words
(1630A/D,
1630G
in
[Edit
Compare]mode)
.
Entire
trace
for
1630G
in
[Full
Compare]
mode
.
Search
:
Memory
may
be
searched
for
any
pattern
defined
within
a
label
set
.
All
pattern
matches
in
memory
may
be
marked
or
separately
displayed
.
Input Specifications
Clock
repetition
rate
Single
Phase
:
25
MHz
with
single
clock
and
single
edge
specified
.
20
MHz
with
any
ORed
combination
of
clocks
and
edges
.
Multiplexed
:
Master
Slave
clock
timing
.
Master
clock
must
follow
slave
clock
by
at
least
10ns
and
preceed
next
slave
clock
by
50
ns or
more
.
Clock
Pulse
Width
:
>_10
ns
at
threshold
.
RC
:
100
kilohms
±2%
shunted
by
approx
5
pF
at
probe
body
.
Setup
time
:
time data
mustbe
present
prior to
clock
transition,
?20
ns
.
Hold
time
:
time data
mustbe
present
after
clock
transition,
0
ns
.
Minimum
swing
:
600
mV
p-p
.
Minimum
input
overdrive
:
250
mV
or
30%
of
input
amplitude,
whichever
is
greater
.
Maximum
voltage
:
±40
volts,
peak
.
Threshold
Range
:
-9
.9
volts to
+9
.9
volts
in
0
.1-volt
increments
.
Accuracy2
.5%
±120
mV
.
Dynamic
Range
:
±10
volts
about
threshold
.
Skew
:
Between
channels
in
onepod
:
56
ns
.
Between
channels
in
different
pods
:
510
ns
.
(These
specifications
are
true
for
input
signal,
VH=-1
.OV,
VL=-1
.6V,
VTH
at-1
.3V,
slew
rate
greater
than
0.25
V/ns
.)
Glitch
:
With
glitch
detection
on,
number
of
timing
channels
are halved
.
Minimum
detectable
glitch
:
5
nsec
width
at
threshold
.
STATE
TIMING
1630A
:
35
0
0 8
27
8
1630D
:
43
0
0
16
35
8
27
16
1630G
:
65
0
0
8
57
8

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HP 1630D Specifications

General IconGeneral
BrandHP
Model1630D
CategoryMeasuring Instruments
LanguageEnglish

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