Section VIII
THEORY OF
OPERATION
Model 3455A
and retains the first data byte information. If the processor
has
read the second
byte of
information
it
stores the com-
posite
of
the first and second bytes and sets the appropriate
output of enundator latches U6S through U70 low (true)
to light the enundator pertaining to the program informa-
tion. The processor next sets the nrfd output (IQ of latch
U1 1 high (true). The output of Ul I is applied to the enable
input
of qualifier gate U13C and to the
driver
A input
ol
transceiver U9 which sets the NRFD bus line low (true).
The processor next sets the ndac output
(6Q)
of latch Ul 1
high
(false).
This
signal is
applied through inverter
UlOA
to the input of qualifier gate U2B to disable it and remove
the interrupt signal to the processor. The ndac
signal is also
applied to the input of gate U13B. The low output of
U13B
is
applied
to the driver B input of transceiver U9 which
stops driving the NDAC
bus line
(allows
it to
go high).
This
indicates to the
HP-IB
controller that the Voltmeter has
accepted the data and is ready for more data.
8-
162. Sensing that the Voltmeter has accepted the data,
the HP-IB controller sets the
DAV
line
high (data on the
DIO
lines is no longer
valid)
and
prepares to output the
next data byte. The
DAV high signal sets the receiver D
output of
transceiver U9 low. The low output of U8 is
applied to the input of gate U ISA to disable it
and through
inverter UlOC to the
input of gate U13C. The high output
of U13C
is applied to the signal input of
buffer
UI5C
and
to the input of interrupt gate U7A.
The low output of U7 A
is applied to the input of gate
U2A to set the interrupt out-
put to the processor.
The processor recognizes the interrupt
signal and enables
buffers UIS and U16 to read the bus
status
word.
8-163.
Upon
determining the nature of
the interrupt, the
processor sets the ndac output
(6Q)
of
latch Ull low
(true). The output of Ul 1 is applied
through inverter UlOA
to the input of qualifier gate U2B
and to the input of gate
UI3B. The high output
of
U13B
is applied to the
Driver
B
input of
transceiver
U9
which sets the NDAC Bus line
low
(true). The processor
then sets the nrfd output (IQ) of
Ull low (false). This
signal is applied to the
driver
A
input
of
U9,
which sets the NRFD bus
line high (false), and to
the
input of
qualifier gate UI3C to
remove
the interrupt
signal. This completes the
sequence for accepting one byte
of
program data.
8-164.
Output Data.
The following paragraphs describe
the
sequence followed
by
the interface circuit to output
measurement data to the HP-IB. The
voltmeter
must
have
previously been
addressed
to “talk" and
the HP-IB must
NOT
be
in
the command mode before the voltmeter can
output
measurement
data.
8-165. When the
Voltmeter
is
addressed to talk the
“dav
rcq” output
(5Q)
of
latch Ull is set high
(true).
As
the
HP-IB exits the
command mode (the ATN signal
is re-
moved) and ail bus
instruments are ready to
accept data
(NRFD is high)
the output of qualifier
gate
U14C
is set
low. The output of UI4C is
applied
to
the input ofbuffer
U16C and the input of
interrupt gate U7C. The
low
output
of U7C is
applied to the input of U2A which
sets the inter-
rupt output to the
processor.
8-166.
Upon
recognizing the interrupt signal, the processor
enables
buffers UIS and UI6 to read the status word. After
determining the nature of the interrupt the
processor
sets
latches
U20 and UI9 to the code of the first byte of mea-
airement data. The outputs of UI9 and U20 are
applied to
the
driver
inputs of
transceivers U6 and U12. The processor
next enables transceivers U6 and UI2 to output
the mea-
surement data to the HP-IB data bus
(DIO
I
through DI07).
After the measurement data
has had time to “settle”, the
processor sets the “dav”
output
(2Q)
of latch Ull high
(true). The
dav
signal
is applied to the input of qualifier
gate U14A
and gate U13D. The high output of UI3D is
applied to the driver D input of
transceiver
U9
which sets
the
DAV
Bus
line low (true). The processor then sets the
dav
req output (SQ)
of
latch Ul 1
low (false). This signal
is
applied to the input of qualifier gate U14C to disable it and
remove the interrupt signal. When the measurement data
byte
has been accepted
by
the receiving instrument(s) the
NRFD line
is
set low and the NDAC line is high. The NDAC
signal sets the Receiver B
output
of
transceiver
U9
iow.
This output is
applied
to the
input
of
qualifier gate UI4B.
The
high
output of U14B is applied to the input of gate
UI4A to enable it. The low output of U14A is applied to
the signal input of UI6D and to the input of interrupt gale
U7C. The low output of U7C is applied to the input of
U2A to set the interrupt output to the
processor.
8-167.
Upon
recognizing the interrupt, the
processor
enables
buffers U16 and U15 and reads the status
word.
After
determining the nature of the interrupt,
the processor
sets the
dav
req output
(5Q)
of latch
U!
1 high. The proces-
sor then sets the dav output
(2Q)
of UlO iow (false). This
signal is applied
to the input of gate U13D
to
remove the
DAV
signal
from the Bus and to the input of qualifier gate
UI4A to remove the interrupt signal. This completes the
output of one data byte. The sequence
is
repeated until
each byte of
measurement
data has been output.
8-168. FRONT PANEL
OPERATION.
8-169.
Circuit
Description.
8-170. Control Switches and
Ennunciatort.
Refer
to
the
Front
Panel Assembly
Schematic for the following
descrip-
tion. Pressing a
front panel key sets
one
of
the input lines
to
priority encoder U57 low.
The output of the encoder is
the octal
equivalent
of
the input line selected
that
is,
the
output when line
“17”
is
set
low
is
111,
when line
“12”
is
low the output
is
010,
etc. The encoder also
sets the gate
output (pin
14)
low to
initiate the processor interrupt cir-
cuit. The outputs of U57
combined with the outputs of
gate USOA
and inverter U49A are applied to the
inputs of
latch US8. The inputs to US8 make up a
code which repre-
sents the key
pressed. The interrupt circuit, after a time
delay
of
approximately 6 ms, sets the
clock input (pin
9)
8-32
To Next Page
Loading...
