HP 37717C - Frequency Offset Tolerance

pdhman.book : pdhapp.doc 51 Tue Oct 14 15:00:20 1997
51
PDH / DSn Testing With The HP 37717C
Frequency Offset Tolerance
Frequency Offset Tolerance
Application
The capability of the network equipment to reliably recover the clock is tested by
varying the clock rate of the generated data and checking for the occurrence of
transmission errors.
The measurement can be made via a loopback or in a cross-multiplexer
configuration, and is generally of short duration.
The ITU G.703 Recommendation for Clock Tolerance is:
• DS1 1.544 Mb/s ± 32 ppm
• E1 2.048 Mb/s ± 50 ppm
• E2 8.448 Mb/s ± 30 ppm
• E3 34.368 Mb/s ± 20 ppm
• DS3 44.736 Mb/s ± 20 ppm
• E4 139.264 Mb/s ± 15 ppm
In SDH systems if the master timing reference is lost a standby reference within 20
ppm can be used for a limited time:
• STM-1 155.520 Mb/s ± 20 ppm
• STM-4 622.080 Mb/s ± 20 ppm.
Default (Known State) Settings
It can be advisable to set the HP 37717C to a known state prior to setting up to make
a measurement. This clears all previous settings and provides a clearly defined
instrument state. For a list of Default Settings and the procedure for accessing them
see Stored Settings in the Mainframe Operating Manual.
Test Setup Procedure (Frequency Offset Tolerance)
If checking frequency offset tolerance at PDH /DSn rates one of the following
options is required.
• UKJ (USA) UKN (USE), or UKK (USB) - Modules with PDH capability
• UKZ - Module with PDH / DSn capability.