HP 8340b User Manual

The
following is
a
general
description
of
PLL1
assemblies:
A36
PLL1
VCO
PLL1
VCO
operates
from
200
to
300
MHz.
Its
output
is divided by
ten
to
provide
the
20
to
30
MHz
signal
required
by
the
YO
loop.
After the
final
divide-by-ten,
the
output
frequency
of the
20-30
loop
becomes:
Fout
=
(Fpiia)/10
+ N1
MHZ-
Fpi,3
can
be
determined
from
the
instrument
diagnostics
by
pressing
[SHIFT] [M3]
and
reading
the
right-hand
FREQUENCY
MHz
display.
If
this
display
reads
0.0000,
the
PLL3/PLL1
path
is
not being
used
in
this
mode,
and
PLL2 is
used
by
itself.
To determine
Fo^,
the
20-30
output
frequency,
press
[SHIFT]
[Ml] and read
the
right
FRE¬
QUENCY
MHz
display.
N1
can
be
calculated from these two
frequencies using
the
above
equation.
As
the
N1
divide
number
changes,
the
gain
of the
loop
amplifier
is
adjusted through
FET
switches
on
the
A36
PLL1
VCO
assembly
to
maintain
a
constant
loop
gain.
The
PLL1
VCO
assembly
also
contains
an output
switch to
select from
one
of
two
20-30
loop
paths;
1.
The
PLL1
VCO
divide-by-ten
is
used
as
the
20-30
output.
PLL2
is
translated
up
through
PLL3
and
PLL1.
2.
The
PLL2
VCO divided
output
is
used
directly.
PLL1
and
PLL3
are
not
used.
The switch positions
are
defined
for
the different
instrument
operating modes
in
the
table
shown on
Figure
C-1.
ASS
PLL1
IF
(Mixer)
The
A38
PLL1
IF
assembly
mixes
the
output
of
PLL1
VCO with
the
output
of
the
PLL3
loop
(Fpll3).
The
frequency
relationships at
the
mixer
are:
F1
=
F2
-
Fp,,3
Where
F1
is
the
PLL1
IF
frequency
and
F2 is
the
PLL1
VCO
frequency.
The
PLL1
VCO
frequency
is:
F2
=
Fp,,3
+
10XN1
MHz
This
shows
that
the
PLL1
VCO
frequency
is
offset
by
10XN1
MHz
from
the
PLL3
output frequency
A37
PLL1
Divider
The
PLL1
phase/frequency detector,
which
resides
on
the
A37
PLL1
divider
assembly,
operates
at
5
MHz.
One
of the
phase detector
inputs
comes
from
a
10
MHz reference
(A29
reference
phase
detec¬
tor
in
the
reference
loop),
which
is
divided
by
two on
the
A37
assembly.
The
second phase
detector
input
is
the
PLL1 IF
output,
after
it
passes
through
a
divide-by-two
and
a
fractional divider.
The
fractional divider
uses
pulse-swallowing techniques
to
divide
by
numbers between
3.60
and
13.97.
It
changes
the
sweeping
IF
signal to
a
fixed
5
MHz signal
that
can
be
phase/frequency
compared
to
the
5
MHz
reference.
When the
loop
is
locked,
both
phase
detector
inputs
are
equal
in
frequency.
The
PLL1
IF
output
is
then
described
by:
F1
=
N1 x
10
MHz,
where
F1
is
the
PLL1
IF
output frequency
(in
MHz) and
N1
is
the
fractional
divide
number (3.60 to
13.97).
C-8
20-30
Loops
Overall
Theory
of
Operation
HP
8340B/41B

HP 8340b Specifications

General

Brand	HP
Model	8340b
Category	Inverter
Language	English