HP 8340b User Manual

Table
F-4.
Diagnostic
SHIFT
M4
Tests
(1
of
2)
Number
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Name
PROCESSOR
TST
ROM
1
CKSUM
ROM
2
CKSUM
ROM
3
CKSUM
ROM
4
CKSUM
RAM
1
RD/WR
RAM
2
RD/WR
EEROM
1
RD/WR
EEROM
2
RD/WR
MKR
RAM RD/WR
PIT
(LED
Registers)
PIT
RESPONDS
I/O
ADDR
BUS
I/O
DATA
BUS
A-D
CONVERTER
LEVEL REF
DAC
MAN SWP
DAC
MARKER RAMP
RESET
DAC
Description
Verifies the
operation
of
the
A60
assembly
processor,
the
Free
Run
DSA,
the
processor's
data and address
bus,
and
a
portion of
the
UV-EROM.
Verifies
the
operation
(checksum)
of
the
UVPROM.
Verifies the
operation
(checksum)
of the
UVPROM.
Verifies
the
operation
(checksum)
of the
UVPROM.
Verifies
the
operation
(checksum)
of the
UVPROM.
Verifies
the
operation
(read/write) of the
RAM.
Verifies the
operation
(read/write)
of the
RAM.
Verifies
the
operation (read/write)
of the
EEPROM,
and
a
portion of
A69U29.
Note
that
this
test is
only
performed
if
A60TP1
RAM
is
grounded.
Verifies
the
operation
(read/write)
of the
EEPROM
and
a
portion
of
A60U29. Note
that
this
test is only performed
if A60TP1
RAM
is
grounded.
Verifies
the
operation
(read/write)
of
the
Address
Register,
the
Sweep
Event
Memory,
the
Read/Write
RAM
Buffer, and
the
Microprocessor Read/
Write
Strobes.
Verifies the
operation
of the timer/self
test
section.
Verifies the
operation
of the
timer/self
test
section.
Verifies
the
operation
of
the
I/O
address
Bus,
the
I/O
Address
bus,
and
a
portion
of the
I/O
Decoding
and
Control.
Verifies
the
operation
of the
I/O
Data
Bus
Buffers,
the I/O
Data
Bus,
and
a
portion
of
the
I/O Decoding
and
Control.
Verifies the
operation
of
the
A27
assembly
ADC
Control
Latch,
the
ADC
Clock/Control,
the
ADC
Input
Multiplexer,
the
Test
ADC,
the
ADC
Window
Comparator,
the
Conversion
Complete
Timer/SRQ
Latch,
and the Status
Buffer.
The
Address
Decoding
is
partially
verified.
Verifies the
operation
of
the
A27
assembly
ALC
Reference Generator
and
a
portion
of
Address
Decoding.
Monitors
LVL
to determine
the
test
results
Verifies the
operation
of the
A57
assembly Manual
Sweep
Dac
and
a
por¬
tion
of the
Microprocessor
And
Read Write
Strobes.
Monitors
LVL
SWP
to
determine
the test
results.
Verifies
the
operation
of
the
A58
assembly.
Monitors
BVSWP
to
determine
the
test
results.
Verifies
the
operation
of the
ASS
assembly.
This
test
specifically
exercises
the
Reset
DAC
and
monitors
BVSWP to
determine
the
test
results.
F.20
A60
Processor
Assembly-Level Troubleshooting
HP
8340B/41B

HP 8340b Specifications

General

Brand	HP
Model	8340b
Category	Inverter
Language	English