HP 8340b - Page 491

PULSE MODULATION ASSEMBLY
A21
Pulse
Modulator
Driver
Pulse
modulation
is
produced
by
the
A21
pulse
modulator driver
assembly
driving
one
of the
two
pulse
modulators.
The
front panel
pulse
modulation
input
is
a
TTL
compatible
input.
A
low
signal
on
this
input
turns
the
RF
off,
and
a
high
turns
the
RF
on.
With
no connection,
the
pulse
modulation input
is
internally
pulled
to
a
TTL
high
level.
When
a
low
signal
is
present on
the
pulse
modulation
input,
the
A21
pulse
modulator driver
delivers
20
mA to
one
of the
two
pulse
modulators.
An
output
multiplexer
on
the
A21
assembly
directs
the
20
mA
modulator
current
to the
A9
low
band
pulse modulator
when
the
instrument
is in
low
band,
or
to
the
pulse
modulator
in
the
A16
mod/splitter
when
the
synthesizer
is in
high
band.
The leveled
instrument pulse
modulation
capability
requires
timing
signals
be
sent
to
the
ALC
assemblies.
The
timing
signals coordinate
the
leveling
operation
with
the
pulse
operation.
When
a
pulse
is
initiated,
three
timing
signals
are
generated on
the
A21
pulse modulator
driver
assembly:
Sample/Hold Timing
This
signal
controls
the
sample/hold
gate
on
the
A25
detector
assembly.
It
is
adjusted
to close
the
gate
(sample)
when
the
RF
pulse
is
on
and
open
the
gate
(hold)
when
the
RF
is
off.
The
sample/
hold
output
voltage
represents
the
peak
RF
amplitude.
Analog to
Digital
Converter
(ADC)
Timing
This
signal
enables
the
analog
to
digital
converter on
the
A27
level
control
assembly
to
monitor
the
output
of the
sample/hold.
The
ADC
is
enabled
when
the
RF is
on,
and for
1
ms
after
the
RF
is
turned off.
After
1
ms,
voltage droop
renders
the
sample/hold
value
inaccurate.
Integrator
Timing
This
signal
controls
the
integrate
and
hold
gate on
the
A26
linear modulator
assembly.
This
gate
is
closed
when
the
RF is
on
and
stable.
To
speed response
time for
narrow pulses,
the
gate
is
held
closed
for
a
minimum of
10ns.
The
sample/hold maintains
a
valid
integrator input
after
the
pulse
is
turned
off
HP 8340B/41B
RF
Section
Theory
of
Operation
H-ll/H-12