HP 8340b User Manual

A34
PI
Pin
I/O
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mnemonic
M5
LMNE
M3
M4
M1
M2
HULM
N6
N5
N4
N3
N2
N1
Levels
TTL (HIGH TRUE)
TTL
(LOW TRUE)
TTL
(HIGH
TRUE)
TTL (HIGH TRUE)
TTL
(HIGH TRUE)
TTL (HIGH TRUE)
TTL (HIGH TRUE)
TTL
TTL
TTL
TTL
TTL
TTL
Source
XA59P1-31
XA59P1-86
XA59P1-32
XA59P1-87
XA59P1-33
XA59P1-88
XA31P1-26
XA59P1-10)
XA59P1-46
XA59P1-102
XA59P1-47
XA59P1-103
XA59P1-48
Destination
XA31P1-15
*
XA31P1-14
XA31P1-29
XA31P1-13
XA31P1-28
XA31P1-26
XA31P1-24
XA31P1-9
XA31P1-25
XA31P1-10
XA31P1-23
XA31P1-8
A34
P2
Pin
I/O
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mnemonic
+20V
+20V
+5.2V
+5.2V
-40V
-40V
-10V
-10V
GND
GND
-5.2V
-5.2V
HULR
Levels
+20V
+20V
+5
2V
+5.2V
-40V
-40V
-10V
-10V
0V
0V
-52V
-5.2V
TTL
(HIGH TRUE)
Source
XA52P1-16,
40
XA52P1-16,
40
XA52P1-17,18,41,42
XA52P1-17,18,41,42
XA53P1-11.30
XA53P1-11.30
XA53P1-12,13,31,32
XA53P1-12,13,31,32
A62 STAR
GND
A62 STAR GND
XA53P1-18,
36
XA53P1-18,
36
XA29P1-7
Destination
*
*
*
*
*
*
«
*
*
*
*
*
XA29P1-7
A
single
letter
in
the
source or
destination column
refers
to
a
function block
on
this
assembly
schematic.
An
asterisk
(*)
denotes
multiple
sources or
destinations;
refer
to the
A34
Reference Loop
-
M/N
Motherboard
Schematic
Diagram for
a
complete
representation
of
signal
sources
and
destinations.
HP 8340B/41B
Assembly-Level
Service
After
Service
Safety
Checks

HP 8340b Specifications

General

Brand	HP
Model	8340b
Category	Inverter
Language	English