HP 8901B - Page 267

Service Model 8901B
an external reference is applied, a detector senses the signal and throws the Time Base Select Switch
to the external position. This switching
is done in such a way as to minimize the interruption of the
reference, since (after
it is divided by five) it is also the Controller clock.
The Time Base Dividers divide the 10 MHz reference by 1600. During a frequency count, Controller
synchronizes itself
to the 6.25 kHz Time Base signal (via the Counter Output and Time Base Gate).
Since the Controller controls the enable period of the Counter (via the Counter Gate Control), the
Time Base signal ultimately determines the Counter accuracy. (The Counter
is enabled for more than
one period of the
6.25 kHz Time Base signal. The number of periods is counted by the Microprocessor
via the Counter Output and Time Base Gate.)
Controller Assembly (A13)
The Controller consists of the Central Processing Unit (CPU), Static Memory Interface (SMI), Read-
Only Memory (ROM), CPU External Register
(or random-access memory, RAM), Memory Select
Decoders, and input/output interface circuitry. The CPU and SMI form the Microprocessor. When
the Controller interfaces with the
HP-IB via the A14 Remote Interface Assembly, the Microprocessor
also includes the Peripheral Input/Output
(PI0 in A14).
The Controller’s program is stored in ROM. To retrieve information from ROM, the SMI, under control
of the CPU, outputs the appropriate address on the Address Bus. Two of the sixteen address bits are
decoded by the Memory Select Decoders to enable one of the ROMs. The fourteen other address bits
address the individual ROMs. The enabled ROM then outputs eight bits of data onto the Data Bus
from the location corresponding to the input address. ROM information may be either a program
instruction
or data. In a similar manner, temporary information is written to or read from RAM. The
RAM is addressed by eight of the eleven address bits;
it inputs or outputs eight data bits.
The RAM is non-volatile, that is, it is not erased when the instrument is powered down or unplugged.
When either the
+12V or +5V Power Supply voltage drops, the +12V and +5V Power Supply Drop
Detector disables the RAM (which prevents
data access for read or write operations), and the Battery
supplies power to the RAM and associated circuits.
The CPU interprets bytes from the ROM as data or instructions depending on the context of the
program.
If the byte is an instruction, the outcome depends on the nature of the instruction. A simple
instruction (such as add
or shift) is executed immediately, and the instruction in the next address is
fetched. More complex instructions fetch additional data or instructions from following addresses and,
in the case of jumps and subroutine calls, cause program execution to move
to another location in
memory.
When a front-panel key is pressed, an interrupt is generated. The interrupt causes program execution
to jump
to a specified address where the interrupt service subroutine is located. The subroutine
interrogates the Keyboard to determine which key
was pressed and then takes the appropriate action.
HP-IB codes and commands interrupt the Microprocessor in a similar way.
The CPU communicates with the SMI and PI0 through the ROM Control (ROMC) lines and the
Data Bus. The CPU manipulates data (arithmetic and logic computations) and contains the clocking
and control circuitry. The clock
is normally derived from the Counter’s Time Base Reference; however,
if the clock fails (to an open circuit) or if the Counter Assembly is unplugged, a clock (internal to the
CPU) will continue to generate clock pulses. The SMI interfaces with the external ROM and RAM.
The CPU also contains bidirectional input/output (I/O) ports to communicate with the instrument’s
hardware via the Instrument Bus. Four
1/0 bits are reserved for servicing of the Controller. Four LEDs
driven from the port indicate errors encountered during power-up verification tests, measurement cycles,
and Keyboard and HP-IB interrupts. Four test points on the port can be used to initiate troubleshooting
routines which use signature analysis. See
Controller Test LEDs and Test Points, paragraph 8-10.
8D-48 Service Sheet BD5