I/O
CO<0..3> Device Select-Code Output Bus
SO<0..3> State/Command Output Bus
DO<0..15> Data Output Bus
SI<0..3> Status Input Bus
DI<0..15> Data Input Bus
CEO Control Enable Output \ initiate I/O, enable device
SIH Service Inhibit \ suppress interrupt
SSI Service Request Strobe Input \ interrupt request
CFI Channel Flag In \ ack/ready from device
SRA Service Request Acknowledge \ interrupt ack
QNR Not service r equest \ interrupt request
QRD Qualifier ROM Disable \ disable proc during IO
QFG Qualifier Flag \ for skip-flag instructions
SCB Set Carry Bit
Q00000 5 LSBits of Q = 0 \ I/O channel 0
DRC Data (IO) Register Clock
TTO T-bus To Output (IOR)
CLC Clear Control bit IO state
STC Set Control bit IO state
CLF Clear Flag IO state
STF Set Flag IO state
SFC Skip if Flag Clear IO state
SFS Skip if Flag Set IO state
OTx Output A/B IO state
LIx Load Into A/B IO state
MIx Merge Into A/B IO state
EOW End Of Word IO state
IOS0 IO State 0
PTF Printer Flag
EBT HPP: Eight-Bit Transfer \ = Q00000
ITS HPP: Input to SBUS \ = LIX+MIX
nTTXENB HPP: T-bus to A/B \ = n(LIX+MIX
Keyboard
KSCANCLK Scan clock
KSCANDET Pressed key detected
KCn Keyboard Columns
KRn Keyboard Rows
nKSTOP STOP key pressed
KLS Keyboard interrupt ack (HP: KB Lights Strobe)
KDBENB Keyboard Data Bus Enable
Display
DEN Display Enable
DOFF Display Off
DCA0..2 Display Column Address
DRELA..G Display Row Enables Left
group
DRERA..G Display Row Enables Right
group
DBANK Display Bank select
DC[0..7][a..e] Display Column drives
Tape Drive
WCL Write CLock
WMK Write MarK
WDT Write DaTa
WDA Write Data channel A
WDB Write Data channel B
RCL Read CLock
RMK Read MarK
RDT Read DaTa
ARA Analog Read channel A
ARB Analog Read channel B
CIN Cassette IN
WPT Write PermiT
BFD Blank Feeder Detect
LDR LeaDeR
CNT CoNtrol Tape
FTC / FAST FasT Cassette
RVC / REV ReVerse Cassette
RNC / RUN RuN Cassette
STOP STOP command
LOAD LOAD register from IO bus
WTC Write To Cassette
CTM ConTrol Mode
nPOPC Power On Pulse Cassette
CTM Control mode
MFW Motor Forward
MRV Motor Reverse
SFW Solenoid Forward
SRV Solenoid Reverse
REN Read Enable
WEN Write Enable
FLG FLaG
INT INTerrupt
DCL Data CLock
Memory
RDM Read Memory
WTM Write Memory
AEN Address ENable
MEN Memory ENable
REF Refresh RAM
RWT Read/WriTe to RAM
REFDLY Refresh Delay
MCP Memory Cycle state-machine flag
MCA Memory Cycle state-machine flag
MCB Memory Cycle state-machine flag
MCC Memory Cycle state-machine flag
MAC Memory ACcess
MTS M register to S-bus
TTM T-bus to M register
M<0..15> M Register (Memory Address)
MR<0..15> Memory Read bus
MRC<0..15> Memory Read bus for Cartridges
MW<0..15> Memory Write bus
ROMB<00..37> ROM Bank select
ROMA<0..8> ROM Address
ROMA<0..8>b ROM Address buffered
RSB1 another version of ROM Bank Select
RAMA<0..9> RAM Address Bits
RAMB<0..7> RAM Bank select
RAMR<a,b> RAM boaRd select
T<0..3> T register outputs
TRI T Register serial Input
TSC T register Serial Clock
TPC T register Parallel load Clock
TMC T register Mode Control \ serial/parallel
EMB Extended Memory Busy
MSTL Memory Suppress T-register Load
EDT External memory Data Transfer
XIN External serial data IN
HP 9830 Computer
Section: Signal Names
Page: A3 Rendition: 2014 Dec 26
CPU Clock
MCK Master Clock \ 8MHz \ HPP: Memory Clock
SCK Shift Clock \ basic bit-serial clock
RCK ROM Clock \ defines one microcode cycle
nCCT
nINH Inhibit Clock \ OC line, normally used by memory
system to stop processor during refresh. Single
stepping control according to patent.
nIHC Inhibit Clock \ turns off internal clock
XTC External Clock
IOCK1 I/O Clock 1 \ for state machine
IOCK2 I/O Clock 2 \ for state machine
IOCKT I/O Clock for transfer from T-bus
CPU Data
RBUS ALU input
SBUS ALU input
TBUS ALU output
A<0..3> A register outputs
B0 B register LSB
E0 E register LSB
P0 P register LSB (program counter)
Q<0..11> Q register outputs (instruction register)
T<0..3> T register outputs
BC Binary Carry flag
DC Decimal Carry flag
CPU Controls
POP Power-On Pulse
MCDIS Microcode DISable
nCCO Control of shift Clock
nIPS
CEM
AC<0..2> ALU function select
UTR Unary to R-bus
PTR P-reg to R-bus
QTR Q-reg to R-bus
BCD BCD ALU operation
XTR A/B-reg to-R-bus
MTS M-reg to S-bus
TTS T-reg to S-bus
SC0 S-bus Selector bit 0
SC1 S-bus Selector bit 1
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