Hardware options installation 45
Memory subsystem architecture
The Intel® Xeon™ 7500 processor memory architecture is designed to take advantage of multiple stages
of memory interleaving to reduce latency and increase bandwidth.
Each Intel Xeon 7500 processor contains two memory controllers as shown in the illustration below. Each
memory controller has two SMI buses operating in Lockstep mode. Each SMI bus connects to a memory
buffer. The buffer converts SMI to DDR3 and expands the memory capacity of the system. Each buffer has
two DDR3 channels and can support up to four DIMMs for a total of eight DIMMs per cartridge.
• Memory speed is not affected by number of DIMMs or ranks. All DIMMs run at the highest possible
speed for a given processor.
• DDR3 memory speed is a function of the QPI bus speed supported by the processor:
o Processors with a QPI speed of 6.4 GT/s run memory at 1066 MT/s.
o Processors with a QPI speed of 5.6 GT/s run memory at 978 MT/s.
o Processors with a QPI speed of 4.8 GT/s run memory at 800 MT/s.
• Successive cache lines are interleaved between the DIMMs and the Lockstep SMI channels of the two
memory controllers in the processor such that adjacent cache lines reside on different memory
controllers, SMIs, DIMMs, and DIMM ranks for better performance. To take advantage of this
feature, DIMMs should be populated evenly between all SMI channels. If an SMI channel pair has
more DIMMs than others, the extra memory on that SMI channel pair does not benefit from the
interleaving mechanism across memory controllers.
Hemisphere mode
The Intel® Xeon™ 7500-series processor architecture incorporates Hemisphere mode, a high-performance
interleaving technology. Hemisphere mode combines the tracking resources of both memory controllers
within each processor for a more aggressive cache line pipelining.
Hemisphere mode is enabled when processors in the system have identical DIMM population behind both
of their memory controllers. That is to say, all populated memory cartridges are populated the same way.
However, there may be different DIMM pairs within each memory cartridge.
• Hemisphere mode is controlled via an RBSU option, enabling the user to select either automatic
(default) or disable.
To Next Page
Loading...
