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3 Reserved 0

2 Reserved 0

1 Reserved 0

0 Reserved 0

Distributed VFD Registers (Read Only) Register offset 04h

Bit 0 of this register is the logic level of the input pin, E_DIST_VFD_PRESENT#.

VFD Registers (Write Only) Register offset 05h

Default Value Of VFD Control Register (before EEPROM is loaded): 07h

Bit 0: Enable/disable the Distributed VFD TX output, i.e. Pin E_D_VFD_TX. This is a write only register and is

set to “1” upon power up/reset. When bit 0 is “1”, the D_VFD_TX output is enabled.

Bit 1: Enable/disable the Integrated VFD TX output, i.e. Pin E_INT_VFD_TX. This is a write only register and

is set to “1” upon power up/reset. When bit 1 is “1”, the INT_VFD_TX output is enabled.

Bit 2: How the D_VFD_TX pin behaves when enabled by bit 0. If bit 2 is “0”, D_VFD_TX will be disabled when

Integrated is present (i.e. when signal INT_VFD_PRESENT# is low). If bit 2 is “1”, D_VFD_TX will be enabled

regardless of the present of Integrated VFD. Bit 2 will be set to “1” upon power up/reset.

Keyboard Control Registers (Write Only) Register offset 06h

Default Value Of Keyboard Control Register (before EEPROM is loaded): 01h

Bit 0: Enable/disable PS/2 keyboard on the planar. When bit 0 is set to “1”, the keyboard will be enabled.

SurePOS 500 Model XX3 Technical Reference, v 1.3 Page 45 of

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IBM 4840-563 Specifications

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