IBM Personal System/2 65 SX - Specifications

Specifications
Number Cycle
Device
of
Walts
Time
(ns)
Microprocessor (16 MHz, 62.5 ns Clock)
Access to System-Board RAM: *
Memory
Read
(Page
Hit)
0
125
Memory
Read
(Anticipated
Page
Miss)
1
187.5
Memory
Read
(Page
Miss)
2
250
Memory
Write
(Page
Hit)
1
187.5
Memory
Write
(Anticipated
Page
Miss)
1
187.5
Memory
Write
(Page
Miss)
2
250
Access to Channel:
Default
Transfer
Cycle
2
250
Synchronous
Transfer
Cycle
4
375
Access
to
ROM
3
312.5
Refresh
Rate
(typically
performed
every
15.1
Ms)
625
(min)
Bus-Master
Access
to
System
Board
RAM
300
(min)
DMA Controller (8 MHz, 125 ns Clock):
Single
Transfer:
375
+
(I/O
Access
+
Memory
Access)
Burst
Transfer:
375
+
(I/O
Access
+
Memory
Access)N
**
System-Board
Memory
Access
375
Default
Transfer
Cycle
250
Synchronous
Transfer
Cycle
375
*
Adapters
installed
in
the
channel
should
not
rely
on
monitoring
system
board
memory
access,
because
channel-memory
control
signals
may
not
be
present
during these accesses.
** N is the number of transfers in the burst.
Figure
1-3.
Performance
Specifications
Note:
The
cycle
times
shown
for
access
to
system
board
RAM
is
based
on
85-
or
100-nanosecond
memory.
°
1-6
Model
65
System
Overview
—
October
1990