IBM Personal System/2 65 SX User Manual

Status Register A (Hex 00A)
Bit Function
7 Update in Progress
6-4 22-Stage Divider
3-0 Rate-Selection Bits
Figure 3-11. Status Register A
Bit7
When
set
to
1,
this
bit
indicates
that
the
time-update
cycle
is in progress.
When
set to 0, it indicates
that the current
date and
time can be read.
Bits6-4
These
bits
identify
which
time-base
frequency
is
being
used.
The
system
initializes
these
bits
to
binary
010,
which
selects
a
32.768-kHz
time
base.
This
is
the
only
value
supported
by
the
system
for
proper
timekeeping.
Bits3-0 These bits allow the selection of a divider output
frequency. The system initializes the rate selection bits to
a binary 0110, which selects a 1.024-kHz, square-wave
output frequency and a 976.562 microsecond
periodic-interrupt rate.
Status Register B (Hex 00B)
Function
Set
Periodic-Interrupt Enable
Alarm-Interrupt Enable
Update-Ended Interrupt Enabled
Square-Wave Enabled
Date Mode
24-Hour Mode
Daylight-Saving Time Enabled
OoOmrNOAADA
Figure 3-12. Status Register B
Bit7
When
set
to
0,
this
bit
updates
the
cycle,
normally
by
advancing
the
counts
at
a
rate
of
one
per
second.
When
set
to
1,
this
bit
immediately
ends
any
update
cycle
in
progress,
and
the
program
can
initialize
the
14
time
bytes
without
any
further
updates
occurring
until
this
bit
is
set
to
0.
Bit
6
This
read/write
bit
allows
an
interrupt
to
occur
at
a
rate
specified
by
the
rate
and
divider
bits
in
Status
Register
A.
When
set
to
1,
this
bit
enables
the
interrupt.
The
system
initializes
this
bit
to
0.
Model 65 System Board — October 1990 3-15

IBM Personal System/2 65 SX Specifications

General

Brand	IBM
Model	Personal System/2 65 SX
Category	Desktop
Language	English