IBM Personal System/2 65 SX - Status Registerc

Bits
Bit 4
Bit 3
Bit 2
Bit1
Bit 0
When
set
to
1,
this
bit
enables
the
alarm
interrupt.
The
system
initializes
this
bit
to
0.
When
set
to
1,
this
bit
enables
the
update-ended
interrupt.
The
system
initializes
this
bit
to
0.
When
set
to
1,
this
bit
enables
the
square-wave
frequency
as
set
by
the
rate-selection
bits
in
Status
Register
A.
The
system
initializes this bit to
0.
This
bit
indicates
whether
the
binary-coded-decimal
(BCD)
or
binary
format
is
used
for
time
and
date
calendar
updates.
When
set
to
1,
this
bit
indicates
the
binary
format.
The
system
initializes
this
bit
to
0.
This
bit
indicates
if
the
hours
byte
is
in
12-hour
or
24-hour
mode.
When
set
to
1,
this
bit
indicates
the
24-hour
mode.
The
system
initializes
this
bit
to
1.
When
set
to
1,
this
bit
enables
the
daylight-saving-time
mode.
When
set
to
0,
this
bit
disables
the
mode
and
the
clock
reverts
to
standard
time.
The
system
initializes
this
bit
to
0.
Status Register C (Hex 00C)
Bit Function
7 Interrupt-Request Flag
6 Periodic-Interrupt Flag
5 Alarm-interrupt Flag
4
Update-Ended-interrupt
Flag
3-0 Reserved
Figure 3-13. Status Register C
Note:
Interrupts
are
enabled
by
bits
6,
5,
and
4
in
Status
Register
B.
Bit 7
Bits
Bit 4
Bits 3-0
When
set
to
1,
this
bit
indicates
that
an
interrupt
has
occurred;
bits
6,
5,
and
4
indicate
the
type
of
interrupt.
When
set
to
1,
this
bit
indicates
that
a
periodic
interrupt
occurred.
When
set
to
1,
this
bit
indicates
that
an
alarm
interrupt
occurred.
When
set
to
1,
this
bit
indicates
that
an
update-ended
interrupt
occurred.
These bits are reserved.
3-16
Model
65
System
Board
~—
October
1990