IBM Personal System/2 65 SX - Page 31

Bit 4
Bit 3
Bits 2-0
available address following the last full 1MB block of
activated system-board memory. When set to 1, this bit
disables system-board RAM between 640KB and 1MB.
This bit determines how addresses hex 0E0000 to
OFFFFF are assigned.
When set to 1, this bit enables ROM; the system assigns
the read-access addresses to ROM and the write-access
addresses to RAM. When set to 0, this bit disables
ROM; the system assigns the read-access addresses to
RAM and disables the write-access addresses. Bit 5 of
this register must be set to 0 before ROM can be
disabled.
When set to 0, this bit sets the memory-access speed to
1, 2, or 3 wait states. When set to 1, this bit sets the
memory-access speed to 0, 1, or 2 wait states. This bit
is set to 0 by a power-on reset. For more information on
memory-access speed, see Figure 1-3 on page 1-6.
These bits select the memory connector to be used by
POS Register 4.
Bits
210
Function
000
001
010-111
Memory Connector 1
Memory Connector 2
Reserved
Figure 2-10.
Memory-Connector Select for POS Register 4
Model 65 POS — October 1990 2-11