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Intel 80287 User Manual
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SYSTEM
CONTROL
AND
INITIALIZATION
The
example
in
Appendix
A
also
illustrates
the
ability
to
allocate
unused
entries
in
descriptor
tables
to
grow
the
tables
dynamically
during
execution.
Using
suitable
naming
conventions,
the
builder
can
allocate
alias
data
segments
that
are
larger
than
the
prototype.
EPROM
version.
The
code
in
the
example
will
zero
out
the
extra
entries
to
permit
later
dynamic
usage.
10-8
pcjs.org
185
187
Table of Contents
Table of Contents
14
Implied Segment Usage by Index, Pointer, and Base Registers
40
Segment Register Selection Rules
45
Status Flags' Functions
62
Control Flags' Functions
63
Interpretation of Conditional Transfers
76
Interrupt Processing Order
104
Dedicated and Reserved Interrupt Vectors in Real Address Mode
106
Processor State after RESET
107
Addressing Segments of a Module Within a Task
129
Descriptor Cache Registers
130
Code and Data Segments Assigned to a Privilege Level
135
Selector Fields
137
Segment Access Rights Byte Format
137
Access Byte Examples
138
Allowed Segment Types in Segment Registers
138
Pointer Privilege Stamping
140
Gate Descriptor Format
143
Call Gate Checks
144
Call Gate
145
Stack Contents after an Inter-Level Call
147
Inter-Level Return Checks
148
Task State Segment and TSS Registers
152
TSS Descriptor
154
Checks Made During a Task Switch
156
Effect of a Task Switch on BUSY and NT Bits and the Link Word
157
Task Gate Descriptor
158
Task Switch through a Task Gate
159
Interrupt Descriptor Table Definition
163
Trap/Interrupt Gate Descriptors
166
Stack Layout after an Exception with an Error Code
167
Trap and Interrupt Gate Checks
168
Interrupt and Gate Interactions
169
Interrupt Descriptor Table Definition
180
Data Type for Global Descriptor Table and Interrupt Descriptor Table
181
Expand-Down Segment
190
Dynamic Segment Relocation and Expansion of Segment Limit
191
Example of NPX Context Switching
194
Table Title Page
350
Comparison Instructions
402
Transcendental Instructions
404
Constant Instructions
406
Processor Control Instructions
407
Instruction Set Reference Information
413
Instruction Execution Time
413
Bus Transfers
414
Instruction Length
415
Programming Facilities
430
High-Level Languages
430
Asm286
432
Defining Data
432
Records and Structures
433
Addressing Modes
434
80287 Emulation
437
Concurrent Processing with the 80287
437
Managing Concurrency
440
Instruction Synchronization
440
Data Synchronization
441
Error Synchronization
442
Incorrect Error Synchronization
444
Proper Error Synchronization
444
System-Level Numeric Programming
445
80287 Architecture
447
Processor Extension Data Channel
447
Real-Address Mode and Protected Virtual-Address Mode
447
Dedicated and Reserved I/O Locations
448
Processor Initialization and Control
448
System Initialization
448
Recognizing the 80287 NPX
448
Configuring the Numerics Environment
450
Initializing the 80287
451
80287 Emulation
451
Handling Numeric Processing Exceptions
452
Simultaneous Exception Response
453
Exception Recovery Examples
453
Conditional Branching Examples
457
Exception Handling Examples
459
Floating-Point to ASCII Conversion Examples
463
Function Partitioning
470
Exception Considerations
471
Special Instructions
471
Description of Operation
471
Scaling the Value
472
In Scaling
472
Avoiding Underflow and Overflow
472
Final Adjustments
473
Output Format
473
Trigonometric Calculation Examples
473
FPTAN and FPREM
473
Cosine Uses Sine Code
474
Machine Instruction Encoding and Decoding
481
Compatibility between the 80287 Npx and the 8087
489
Implementing the Ieee P754 Standard
493
Options Implemented in the 80287
495
Areas of the Standard Implemented in Software
495
Additional Software to Meet the Standard
496
Glossary of 80287 and Floating-Point Terminology
499
Index
507
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Intel 80287 Specifications
General
Brand
Intel
Model
80287
Category
Computer Hardware
Language
English
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