Intel 80287 - Page 53

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80286

BASE

ARCHITECTURE

80188

8ASIC INSTRUCTION SET

80286

EXTENDED INSTRUCTION SET

SYSTEM CONTROL INSTRUCTION SET

G30108

Figure 2-15. Hierarchy of Instructions

2-27

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Table of Contents14
Implied Segment Usage by Index, Pointer, and Base Registers40
Segment Register Selection Rules45
Status Flags' Functions62
Control Flags' Functions63
Interpretation of Conditional Transfers76
Interrupt Processing Order104
Dedicated and Reserved Interrupt Vectors in Real Address Mode106
Processor State after RESET107
Addressing Segments of a Module Within a Task129
Descriptor Cache Registers130
Code and Data Segments Assigned to a Privilege Level135
Selector Fields137
Segment Access Rights Byte Format137
Access Byte Examples138
Allowed Segment Types in Segment Registers138
Pointer Privilege Stamping140
Gate Descriptor Format143
Call Gate Checks144
Call Gate145
Stack Contents after an Inter-Level Call147
Inter-Level Return Checks148
Task State Segment and TSS Registers152
TSS Descriptor154
Checks Made During a Task Switch156
Effect of a Task Switch on BUSY and NT Bits and the Link Word157
Task Gate Descriptor158
Task Switch through a Task Gate159
Interrupt Descriptor Table Definition163
Trap/Interrupt Gate Descriptors166
Stack Layout after an Exception with an Error Code167
Trap and Interrupt Gate Checks168
Interrupt and Gate Interactions169
Interrupt Descriptor Table Definition180
Data Type for Global Descriptor Table and Interrupt Descriptor Table181
Expand-Down Segment190
Dynamic Segment Relocation and Expansion of Segment Limit191
Example of NPX Context Switching194
Table Title Page350
Comparison Instructions402
Transcendental Instructions404
Constant Instructions406
Processor Control Instructions407
Instruction Set Reference Information413
Instruction Execution Time413
Bus Transfers414
Instruction Length415
Programming Facilities430
High-Level Languages430
Asm286432
Defining Data432
Records and Structures433
Addressing Modes434
80287 Emulation437
Concurrent Processing with the 80287437
Managing Concurrency440
Instruction Synchronization440
Data Synchronization441
Error Synchronization442
Incorrect Error Synchronization444
Proper Error Synchronization444
System-Level Numeric Programming445
80287 Architecture447
Processor Extension Data Channel447
Real-Address Mode and Protected Virtual-Address Mode447
Dedicated and Reserved I/O Locations448
Processor Initialization and Control448
System Initialization448
Recognizing the 80287 NPX448
Configuring the Numerics Environment450
Initializing the 80287451
80287 Emulation451
Handling Numeric Processing Exceptions452
Simultaneous Exception Response453
Exception Recovery Examples453
Conditional Branching Examples457
Exception Handling Examples459
Floating-Point to ASCII Conversion Examples463
Function Partitioning470
Exception Considerations471
Special Instructions471
Description of Operation471
Scaling the Value472
In Scaling472
Avoiding Underflow and Overflow472
Final Adjustments473
Output Format473
Trigonometric Calculation Examples473
FPTAN and FPREM473
Cosine Uses Sine Code474
Machine Instruction Encoding and Decoding481
Compatibility between the 80287 Npx and the 8087489
Implementing the Ieee P754 Standard493
Options Implemented in the 80287495
Areas of the Standard Implemented in Software495
Additional Software to Meet the Standard496
Glossary of 80287 and Floating-Point Terminology499
Index507

Intel 80287 - Page 53

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