MEMORY INTERFACING
6.2.6
EPROM
Interface
Figure 6-6
shows
the signal timing for bus cycles from an 80386 operating
at
16
MHz
to a
27128-1 EPROM, which has a ISO-nanosecond access time. Faster 11O-nanosecond EPROMs
are also available but
in
this design, they require the same number of wait states as the
ISO-nanosecond EPROMs require. Timings for a ISO-nanosecond SRAM are included for
comparison.
In the EPROM interface, the OE# input of each EPROM devices
is
connected directly to
the MRDC# signal from the bus controller. The wait state requirement
is
calculated by
adding up worst-case delays and comparing the total with the 80386 bus cycle time.
The bus cycle timings can be calculated from the waveforms
in
Figure
6-6.
In the following
example, the timings for
I/O
accesses are calculated for CLK2 =
32
MHz and B-series
PALs. All times are
in
nanoseconds. Check the most recent 80386 Data Sheet to confirm
all parameter values.
tAR: Address stable before Read (MRDC# fall)
(1
x CLK2
period)-
PAL RegOut
Max-
Latch Enable Max
- PAL RegOut Min
(1
x 31.25) -
12
- 11.5
+0
= 7.75 nanoseconds
tRR: Read (MRDC#) pulse width
(4 x CLK2 period)
(4 x 31.25)
=
113
nanoseconds
- PAL RegOut Max + PAL RegOut Min
-12
+ 0
tRA: Address hold after Read (MRDC# rise)
(0 x CLK2 period) - PAL RegOut Max + PAL RegOut Min
+ Latch Enable Min
(0 x 31.25) -
12
+ 0
+ 5
=
-7
nanoseconds (This
is
acceptable because latched addresses are held for at
least as long as the end of the bus cycle.)
tAD: Data delay from Address
(6 x CLK2 period)
- xcvr. prop. Min
(6 x 31.25)
- 6
=
148
nanoseconds
-
PAL
RegOut Max - Latch Enable Max
- 80386 Data Setup Min
-
12
- 11.5
-
10
6-9
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