TAG
O
FF
001
1-'-9
BITS-!
32KS
CACHE SUBSYSTEMS
32·BIT
1
31
24 23 15 14
PROCESSOR ICACHEIDRAM
TAG
INDEX
ADDRESS SELECT
I+-
2 x
32K
SRAM = 15
BITS-l
1-16
MEGABYTE
DRAM
=24
BITS-j
DATA
INDEX
7FFC
7FF8
00,"
1
OOOC
0008
0004
0000
24682468
11223344
DATA
INDEX
TAG
DATA
24682468
~
7FFC
001
12345678
f-J
7FF8
lFF
11223344
0010
-
-
OOOC
-
7FFC
7FF8
0008
000
87654321
I
1-
l-+
0004
001
11235813
12345678
77777777
~
0000
000
13579246
I-
0010
OOOC
1+32BITS-Pj
1+9
BITS-!
~32BITS+l
RAM
32KSRAM
-
0008
11235813 0004
77777777 0000
7FFC
1
7FF8
0010
OOOC
0008
0004
0000
64K CACHE
87654321
13579246
f4-32
BITS..j
16 MEGABYTE
DRAM
Figure 7-4. Two-Way Set Associative Cache Organization
TAG
IF
00
00
G30107
The set associative cache, however,
is
more complex than the direct mapped cache. In the
2-way set associative cache, there are two locations in the cache
in
which each block can be
stored; therefore, the controller must make two comparisons
to
determine
in
which block, if
any, the requested data
is
located. A set associative cache also requires a wider tag field,
and thus a larger SRAM
to
store the tags, than a direct mapped cache with the same amount
of cache memory and main memory. In addition, when information
is
placed into the cache,
a decision must be made
as
to which block should receive the information.
7-7
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