MUL
TIBUS®
I AND
80386
9.2.2
Address Decoder
A
MUL
TIBUS I system typically has both shared and local memory.
I/O
devices can also
be located either
on
MUL
TIBUS I or a local bus. Therefore, the address space of the 80386
must be allocated between
MUL
TIBUS I and the local bus, and address decoding logic
must be used to select one bus or the other.
The following
two
signals are needed for MULTIBUS I selection:
• Bus Size
16
(BS16#) must be returned active to the 80386 to ensure a 16-bit bus cycle.
Additional terms for other devices requiring a 16-bit bus can be added to the
BS
16# PAL
equation.
•
MUL
TIBUS Enable (MBEN) selects the 82288
Bus
Controller and the 82289
Bus
Arbiter
on the
MUL
TIBUS I interface. Other outputs of the decoder PAL are programmed to
select memory and
I/O
devices
on
the local bus.
The decoding of addresses to select either the local bus or the
MUL
TIBUS I
is
straight
forward. In the following example, the system uses the first
64
megabytes of the 80386
memory address space, requiring
26
address
liries.
The
MUL
TIBUS I memory
is
allocated
to the addresses from
FOOOOOH
to F3FFFFH. The same PAL equation generates the two
PAL
outputs BSI6# and MBEN:
/A25
*
/A24
* A23 * A22 *
A2l
* A20 *
/A19
* /A18
I/O
resources residing
on
MULTIBUS I can be memory-mapped into the memory space of
the 80386 or I/O-mapped into the
I/O
address space independent of the physical location
of
the devices
on
MULTI BUS I. The addresses of memory-mapped
I/O
devices must be
decoded to generate
I/O
read or
I/O
write commands for memory references that fall within
the I/O-mapped regions of the memory space. This technique
is
discussed
in
Chapter 8
along with the tradeoffs between memory-mapped
I/O
and I/O-mapped
I/O.
9.2.3
Wait-State Generator
The wait-state generator controls the READY # input of the 80386. For local bus cycles, the
wait-state generator produces signal outputs that correspond to each wait state of the 80386
bus cycle, and the PAL READY # output uses these signals to set READY # active after the
required number of wait states. Two of the wait-state signals, WSI and WS2, are also used
to generate
SO#
and
Sl#.
READY# generation for
MULTI
BUS I cycles
is
linked to the Transfer Acknowledge
(XACK#) signal, which
is
returned active by the accessed device
on
MUL
TIBUS I when
the
MULTI
BUS I cycle
is
complete. For a system containing a
MULTI
BUS I interface as
well as a local bus, XACK# must be incorporated into the wait-state generator to produce
the READY # signal. The necessary logic
is
shown
in
Figure 9-3.
9-5
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