MUL TIBUS® I
AND
80386
• Mode 2
is
suited for a subsystem that
is
one of several subsystems
that
are all equally
likely to require
MUL
TIBUS
I.
The performance decrease caused
by
the delay necessary
to take control of
MULTIBUS I
is
distributed evenly to all subsystems.
• Mode 3 should be used for a subsystem that uses MUL TIBUS I frequently. The delay
required for taking control of
MUL TIBUS I and the consequent performance decrease
is
shifted to subsystems that use MULTI BUS I less often.
• Switching between modes 2 and 3
is
useful if the subsystem demand for
MUL
TIBUS I
is
unknown or variable.
9.4.3
MUL TIBUS® I Locked Cycles
Locked bus cycles for the local bus are described in Chapter
3.
In
locked bus cycles, the
80386 asserts the LOCK# signal to prevent another bus master from intervening between
two
bus cycles.
In
the same manner, an 80386 processing subsystem can assert the LLOCK#
output of its bus arbiter to prevent other subsystems from gaining control of MULTIBUS
I.
A locked cycle overrides the normal operating mode of the bus arbiter (one of the four
modes mentioned above).
Locked
MULTI BUS I cycles are typically used to implement software semaphores (described
in
Chapter 3) for critical code sections or critical real-time events. Locked cycles can also
be used for high-performance transfers within one instruction.
The
80386 initiates a locked MULTI BUS I cycle by asserting its LOCK# output to the
82289 bus arbiter. The bus arbiter outputs its
LLOCK# signal to the MULTIBUS I LOCK#
status line and holds LLOCK# active until the LOCK# signal from the 80386 goes inactive .
. The
LLOCK# signal from the bus arbiter must be connected to the MUL TIBUS I LOCK#
status line through a tristate driver controlled
by
the AEN# output of the bus arbiter.
9.5
OTHER MUL TIBUS® I DESIGN CONSIDERATIONS
Additional design considerations are presented in this section. These considerations include
provisions for interrupt handling, 8-bit transfers, timeout protection, and power failure
handling
on
MUL
TIBUS
I.
9.5.1
Interrupt-Acknowledge
on
MUL TIBUS® I
When an interrupt
is
received
by
the 80386, the 80386 generates an interrupt-acknowledge
cycle (described in Chapter 3) to fetch an 8-bit interrupt vector from the 8259A Program-
mable Interrupt Controller. The 8259A can be located
on
either MULTIBUS I or a
local bus.
9-14
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