MUL
TIBUS®
I AND
80386
Multiple 8259As can be cascaded (one master and up to eight slaves) to process up to
64
interrupts. Three configurations are possible for cascaded interrupt controllers:
• All of the interrupt controllers for one 80386 reside
on
the local bus of that processor,
and all interrupt-acknowledge cycles are directed to the local bus.
• All slave interrupt controllers (those that connect directly to interrupting devices) reside
on
MUL
TIBUS I. The master interrupt controller may reside
on
either the local bus or
MUL
TIBUS
I.
In this case, all interrupt-acknowledge cycles are directed to
MULTIBUS
I.
• Some slave interrupt controllers reside
on
local buses, and other slave interrupt control-
lers reside
on
MUL
TIBUS
I.
In this case, the appropriate bus
for
the interrupt-
acknowledge cycle depends
on
the cascade address generated by the master interrupt
controller.
In the first two configurations,
no
decoding
is
needed because all interrupt acknowledge
cycles are directed to one bus. However, if a system contains a master interrupt controller
residing
on
a local bus and
at
least one slave interrupt controller residing
on
MULTIBUS I,
address decoding must select the bus for each interrupt-acknowledge cycle.
The interrupt-acknowledge cycle must be considered
in
the design of this decoding logic.
The 80386 responds to an active
INTR
input by performing two bus cycles. During the first
cycle, the master interrupt controller determines which, if any, of its slave controllers should
return the interrupt vector and drive sits cascade address pins (CASO#, CASl#, CAS2#) to
select
that
slave controller. During the second cycle, the 80386 reads an 8-bit vector from
the selected interrupt controller and uses this vector to service the interrupt.
In a system that has slave controllers residing
on
MUL
TIBUS I, the circuit shown
in
Figure 9-9 can be used to decode the three cascade address pins from the master controller
to select either
MUL
TIBUS I or the local bus for the interrupt-acknowledge cycle.
If
MUL
TI:SUS I
is
selected, the 82289 Bus Arbiter
is
enabled. The 82289
in
turn requests
control of MULTIBUS I and enables the address and data transceivers when the request
is
granted.
The bus-select signal must become valid for the second interrupt-acknowledge cycle. The
master controller's cascade address outputs become valid within
565
nanoseconds after the
INTA#
output from the bus control logic goes active. Bus-select decoding requires
30
nanoseconds, for a total of
595
nanoseconds from INTA# to bus-select valid. The four idle
bus cycles that the 80386 automatically inserts between the
two
interrupt-acknowledge cycles
provides some of this time. The wait-state generator must add wait states to the first
interrupt-acknowledge cycle to provide the rest
of
the time needed for the bus-select signal
to become valid.
The cascade address outputs are gated onto
A8;
A9, and AlO of the address bus through
three-state drivers during the second interrupt-acknowledge cycle. Bus control logic must
generate a Master Cascade Enable
(MCE)
signal to enable these drivers. This signal must
remain valid long enough for the cascade address to be captured
in
MUL
TIBUS I address
latches; however it must be de-asserted before the 80386 drives the address bus.
9-15
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