Intel 80386

MUL TIBUS® I AND 80386
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~
l"""- I"""-
a
r- C a - READY#
ALE
D
'-
D
CLK2
Q Q
'-- '--
TIMEOUT#
G30107
Figure 9-11. Bus-Timeout Protection Circuit
The iLBX™ Bus Specification describes the iLBX Local Bus Expansion standard in detail.
The iLBX bus interface requires the generation of AI, AO, and BHE# from the 80386
BE3#-BEO# outputs. The iLBX connector contains 24 address bits (AB23-ABO) and 16 data
bits (DBI5-DBO), which are taken from the buffered address lines (A23-AO), and data lines
(DI5-DO) of the 80386 local bus. BHE# is inverted and buffered to provide the Byte High
Enable (BHEN) signal.
The Read/Write (R/W#), Data Strobe (DSTB#), and Address Strobe (ASTB#) controls
are generated from local bus control signals using the logic shown in Figure 9-12. R/W# is
a delayed, inverted version of the W /R# output of the 80386. DSTB# goes active when
either RD# or WR# from the local bus control goes active. ASTB# and DSTB# are delayed
to allow adequate setup time for BHEN. In this example, the WS2 signal, which is active
during the third CLK cycle of the 80386 bus cycle, provides the delay.
A chip-select output of address decoding logic goes active for accesses to the memory and
I/O locations allocated to the iLBX bus and selects the iLBX address and data buffers.
Command signals from the local bus control logic enable the outputs of the iLBX
transceivers.
When an iLBX cycle is complete, the Acknowledge (ACK#) signal is returned over the
iLBX bus. This signal must be synchronized and incorporated into the wait-state generator
logic to provide the READY # signal.
9.7 DUAL-PORT RAM WITH MUL TIBUS® I
A dual-port RAM is a memory subsystem that can be accessed by both the 80386, through
its local bus, and other processing subsystems, through the MULTI BUS I system bus. Dual-
port RAM offers some of the advantages of both local resources and system resources. It is
an effective solution when using only local memory or only system memory would decrease
system cost and/or performance significantly.
9-19