MUL TIBUS® I
AND
80386
Suppose the 80386 locks an access to dual-port RAM followed by a MULTIBUS access, to
ensure
that
the accesses are performed back-to-back. (This could happen only
in
protected
mode during interrupt processing when the IDT
is
in
the dual-port RAM and the target
descriptor
is
in
MULTI BUS RAM.)
At
the same time the 80386 performs the first locked
cycle, another device gains control of
MUL
TIBUS I for the purpose of accessing dual-port
RAM. The 80386 cannot gain control of MULTI BUS I to complete the locked operation,
and the other device cannot relinquish control
of
MUL TIBUS I because it cannot complete
its access to dual-port RAM. Each device therefore enters an interminable wait state.
Two approaches can be used to avoid deadlock:
• Requiring software to be free of locked accesses to dual-port RAM.
• Designing hardware to negate the LOCK# signal for transfers between dual-port
RAM
and
MUL
TIBUS I.
If
this approach
is
used, software writers must be informed that such
transfers
will
not be locked even though software dictates locked cycles.
9-21
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