PHYSICAL DESIGN AND DEBUGGING
Logic analyzer connection points should be provided to all 80386 address outputs
(A2-A31 and BEO#-BE3#) even if there are not enough logic analyzer inputs to accom-
modate all of them. Initially, only
BEO#,
BEl
#,
BE2#, BE3#, and the output of the address
decoder circuit should be connected. The single output of an address decoder circuit
represents many bits of address information.
If
the address decoder does not work as
expected, more of the logic analyzer inputs should be moved to the 80386 address pins.
• Buffers and visual indicators (such
as
LEDs) for three or four of the critical 80386 control
signals. A visual indicator for the ADS# output, for example, will light when the system
is
performing bus cycles.
11.5.2
Bus
Interface
During initial debugging, bus-cycle operation should be simplified. The 80386 bus interface
is
flexible enough to be tested
in
stages. To simplify bus control, the initial testing should be
performed with a non-pipelined address. The NA# input should be tied high (negated) to
guarantee
no
address pipelining. The only signals that need to
be
controlled are the READY #
input and the BSI6# input.
The READY # input
on
the 80386 lets the user delay the end of any bus cycle for as long as
necessary. For each CLK cycle after T2 that READY #
is
not sampled active, a wait state
is
added. READY# can be used to provide extra time (wait states) for
slow
memories or
peripherals. Wait state requirements are a function of the device being addressed. Therefore,
the address decoder must determine
how
many wait states, if any, to add to each bus cycle.
The address decoder circuit (usually
in
conjunction with a shift register) must generate the
READY # signal when it
is
time for the bus cycle to end.
It
is
critical
for
the system to
generate the READY # signal; if it does not, the 80386
will
wait forever for the bus cycle to
end.
EPROMs, static RAMs, and peripherals all interface
in
much the same
way.
The
EPROM
interface
is
the simplest because EPROMs are read-only devices. RAM interfaces must
support byte addressability during
RAM
write cycles. Therefore,
RAM
write enables for
each byte of the 32-bit data bus must
be
controlled separately.
The BS16# signal must be activated when the current bus cycle communicates over a 16-bit
bus. An address decoder circuit can be used to determine if
BS
16# must be asserted during
the current bus cycle.
11.5.3 Simplest Diagnostic Program
To start debugging 80386 hardware, the user should make a set of EPROMs containing a
simple program, such
as
a 4-byte diagnostic that loops. Such a program
is
shown in
Figure 11-11. Because the program
is
four bytes long, it will exercise all
32
bits of the data
bus. This program tests only the code prefetch ability of the 80386.
In generating this program, the user should take into account the initial values of the
80386 CS register
(FOOOR)
and IP register (FFFOR) after reset. The software entry point
(label
START
in
Figure 11-11) must match the CS:IP location.
11-11
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