PHYSICAL DESIGN
AND
DEBUGGING
3.
Tie the 80386 INTR, NMI, and HOLD input pins
low.
Tie the READY # pin high
so
that the first bus cycle will not end. Reset the 80386, and check that the 80386
is
emitting
the correct signals to perform its first code fetch from physical address FFFFFFFOH.
Connect the address latch, and verify that the address
is
driven
at
its outputs.
4.
Connect the address decoding hardware
to
the 80386, and check that after reset, the
80386
is
attempting to select the EPROM devices
in
which the initial code to be executed
will be stored.
5.
Connect the data transceiver to the system, and check that after reset, the transceiver
control pins are being driven for a read cycle. Connect all address pins of the
EPROM
sockets, and check that after reset, they are receiving the correct address for the first code
fetch cycle.
Intel's
iPPS programmer for EPROMs supports dividing an object module into four
EPROMs,
as
is
necessary for a 32-bit data bus to EPROM. The programmer can also divide
an object module into two
EPROMs for a 16-bit data bus to the EPROMs. (In this case,
the BS16# input to the 80386 must be asserted during all bus cycles communicating with
the
EPROMs).
When the 82384, crystal, 80386, address decoder, address latch, data transceiver, and
READY # generation logic (including wait-state generation) are functioning, the 80386
is
capable of running the software
in
the EPROMs. Now the simple debug program described
above can be run to see whether the parts of the system work together.
After installing the
EPROMs, the READY # line should be tied high (negated)
so
that the
80386 begins its first bus cycle after reset and then continues to add wait states. While the
system
is
in
this state, the circuit should be probed to verify signal states, using a voltmeter
or oscilloscope probe.
The programmer should check whether the address latches have latched the first address
and whether the address decoder
is
applying a chip-select signal to the EPROMs. The
EPROMs should be emitting the first four opcode bytes of the first code to be executed
(90H,
90H, EBH,
FCH
for the 4-byte program of Figure 11-11), and the opcode should be
propagating through the data transceivers to the 80386 data pins.
Then the READY # input should be connected to the READY # generation logic, the 80386;
and the results should be tested when the simple program runs. Because the program loops
back
on
itself, it runs continuously.
At
this point, the system has progressed to running
multiple bus cycles,
so
a logic analyzer
is
needed to observe the dynamic behavior of the
system.
When the
RPROMs programmed with the simple 4-byte diagnostic program are installed
and the 80386
is
executing the code, the LED indicator for ADS# (if included
in
the system)
glows, because ADS#
is
generated for each bus cycle
by
the 80386.
It
is
necessary to check
that the
EPROMs are selected for each code fetch cycle. After system operation
is
verified
with the simple program, more complex programs can be run.
11-13
To Next Page
Loading...
