Intel 80386

TEST CAPABILITIES
state of bit 0 in the command register. If bit 0 = 1, a TLB lookup operation is performed.
If bit 0 = 0, a TLB write is performed.
The tag bits (not including the linear address) consist of the following:
Bit Name
Definition
11 Valid (V) Entry is valid
10 Dirty (D) Entry has been changed
9
Not Dirty (D#) Entry has not been changed
8
User (U) Entry is accessible to User privilege level
7 Not User (U#) Entry is not accessible to User privilege level
6
Writable (W) Entry may be changed
5 Not Writable (W#)
Entry may not be changed
The complement of the Dirty, User, and Writable bits are provided to force a hit or miss for
TLB lookups. A lookup operation with a bit and its complement both
low is forced to be a
miss; if both bits are high, a hit
is forced. A write operation must always be performed with
a bit and its complement bit having opposite values.
The data register has the format shown in Figure 12-2 (bottom). The replacement pointer
indicates which of the four sets of the TLB
is to receive write data. Its value is changed
according to a proprietary algorithm after every TLB hit. For testing, a TLB write may use
the replacement pointer value that exists in the TLB, or it may use the value in bits 3 and 2
of the data register.
If data register bit 4 = 0, the existing replacement pointer is used. If
bit 4 = 1, bits 3 and 2 of the data register are used.
The TLB write operation progresses
as follows:
1. The physical address, replacement bit, and replacement pointer value (optional) are written
to the data register.
2. The linear address and tag values are written to the command register, as well as a 0
value for bit O.
It is important not to write the same linear address to more than one TLB entry.
Otherwise, hit information returned during a TLB lookup operation
is undefined.
The TLB lookup operation progresses
as follows:
• The linear address and tag values are written to the command register, as well as a
1 value for bit
O.
• New values for the hit/miss bit and replacement pointer are written to bits 4-2 in the
data register. If the hit/miss bit (bit 4) is 1, bits 31-12 contain the physical address from
the TLB. Otherwise, bits 31-12 are undefined.
12-4