APPENDIX A
LOCAL
BUS
CONTROL
PAL
DESCRIPTIONS
The bus controller
is
implemented
in
two
PALs. One PAL (called PAL-I)
follows
the 80386
bus cycles and generates the overall bus cycle timings. The second PAL (PAL-2) generates
most of the bus control signals.
The
PALs are clocked
by
CLK2. They could also be clocked
by
CLK. Using CLK2 has the
following advantages over using CLK:
• The skew from clock to command signal
is
reduced,
so
higher performance
is
possible
with slower devices.
• The 80386 ADS# and READY # signals can be sampled directly.
If
CLK were used, it
would be possible to sample
ADSO# from the 82384 instead of ADS#, but the READY #
generation logic would be more complex because READY # must be synchronized to
CLK2.
• The PAL can provide delays
in
31-nanosecond, rather than 62-nanosecond, increments.
The advantages of using CLK to clock the
PALs are
as
follows:
• A slower PAL device could be used.
• One PAL input
is
saved because only CLK,
rClther
than CLK and CLK2,
is
needed.
Because CLK2
is
used to clock the PALs, the choice of PALs
is
currently limited to only
20-pin B-series PALs.
PAL-1 FUNCTIONS
PAL-l
is
implemented
as
two
main state machines. The BUSSTATE state machine, which
is
used to follow the 80386 bus cycles,
is
specified by the state of
two
signals, IDLE and
PIPE, and
follows
the 80386 bus by sampling ADS# and READY
#.
IDLE and
PIPE
are
often useful
in
implementing other 80386 subsystems (such
as
the DRAM controller described
later
in
this book).
The
LOCALST A TE state machine keeps track of the local bus state and
is
specified
by
signals L2,
Ll,
and
LO.
Although the local bus state usually follows the 80386 bus state,
so
that
the LOCALSTATE and BUSSTATE states are the same, there are times when the
local bus cycle lags the
80386 bus cycle
in
order to handle data-float and peripheral recovery
times correctly. Therefore, it
is
easier to implement this PAL using the
two
separate state
machines.
LOCALST ATE uses the 80386 W jR# signal and various chip-select inputs to
determine what type of cycle to run.
A third, simpler state machine
is
also implemented
in
PAL-I. Q 1 and
QO
comprise a
SEQUENCE
counter that
is
used to implement the various time delays required by the local
bus state machine.
A-1
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