Intel 80386

LOCAL BUS CONTROL PAL DESCRIPTIONS
The NA# output of PAL-I activates address pipelining for the I/O and l-wait-state devices.
For O-wait-state devices, external logic generates NA#, because these devices require NA#
sooner than P AL-I can generate it.
PAL-2 FUNCTIONS
PAL-2 generates most bus control signals, including all five command signals, the READY #
signal, and the latch and transceiver enable signals. PAL-2 inputs the three LOCALST ATE
signals from PAL-I and the three
80386 bus cycle definition pins (MIO#, DC#, and WR#)
in order to follow the local bus state. PAL-2 also inputs the O-wait-state chip-select signal
in order to set output signals quickly enough for zero wait states.
Note that the transceiver direction enable (DT
/R#) is simply a latched version of W /R#.
This saves a PAL output and also guarantees that the transceiver direction does not change
while DEN#
is enabled.
PAL EQUATIONS
The equations for PAL-I and PAL-2 are shown in Figures A-I and A-2, respectively. These
equations are shown
in a high-level PAL language (ABEL, by Data I/O) that allows the
PAL to be described
as a series of states rather than equations. This language frees the
designer of the tedious task of implementing the state machine and reducing the logical
equations manually. The language saves time not only
in the initial design, but also in
debugging the state machines. The automated term reduction of the high-level PAL language
allows the designer to explore many implementations quickly, which
is a useful feature for
complex PAL designs.
Figures A-3 and A-4 show the PAL equations for PAL-I and PAL-2 using PALASM
by
Monolithic Memories.
A-2