SYSTEM OVERVIEW
1.4
CACHE CONTROLLER
A cache memory subsystem provides fast local storage for frequently accessed code and
data. This results
in
faster memory access for the microprocessor and reduces the amount
of traffic
on
the system bus.
The 82385 Cache Controller
is
a high performance peripheral design!!p s,pecifically for the
80386. The 82385 allows the
80386 to reach its full performance potential by offering the
following features:
* Supports a
32
kbyte cache memory organized
as
either 2-way set associative or direct
mapped.
'I'
Integrated cache directory and management logic.
* Utilizes posted writes for zero wait states
on
write cycles.
* Guarantees cache coherency
by
bus watching.
* Supports non-cacheable accesses.
* Presents an 80386 interface to system resources.
* Dhrystone benchmark
shows
an average hit rate of
95%.
1.5
CLOCK GENERATOR
The 82384 Clock Generator generates timing for the 80386 and its support components.
The 82384 provides both the
80386 clock (CLK2) and a half-frequency clock (CLK) to
indicate the internal phase of the
80386 and to drive 80286-compatible devices that may be
included
in
the system.
It
can also be used to generate the RESET signal for the 80386 and
other system components. Both CLK2 and CLK are used throughout this manual to describe
execution times.
1.6
8086/80286
FAMILY COMPONENTS
With the appropriate interface, the 80386 can use 8086/80286 family components. These
components include the 8259A and 82258.
The 8259A Programmable Interrupt Controller manages interrupts for
an
80386 system.
Interrupts from
as
many
as
eight external sources are accepted
by
one 8259A;
as
many
as
64
requests can be accommodated by cascading several 8259A chips. The 8259A resolves
priority between active interrupts, then interrupts the processor and passes a code to the
processor to identify the interrupting source. Programmable features of the 8259A allow it
to be used
in
a variety of ways to fit the interrupt requirements of a particular system.
1-5
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