APPENDIX C
DRAM
PAL DESCRIPTIONS
This section describes the inputs, outputs, and functions of each of the PALs in the DRAM
design described
in
Chapter
6.
The terms Start-Of-Phase and Middle-Of-Phase used to
describe
PAL input sampling times refer to the 80386 internal CLK phase and are defined
in
Figure
C-l.
The setup, hold, and propagation delay times for each PAL input and output can be deter-
mined from the
PAL data sheets. In a
few
cases, the setup and hold times during certain
events must be violated;
in
these cases, the PAL equations mask these inputs
so
they are not
sampled. Because the states are fully registered and because inputs are masked when their
setup or hold times cannot be guaranteed,
no
hazards exist.
DRAM STATE PAL
The DRAM State PAL determines when
to
run a
new
DRAM cycle and tracks the state of
the DRAM through the cycle. The inputs sample DRAM requests from the processor (or
any other bus master)
as
well
as
requests for refresh. The outputs store state information
and generate the
two
RAS signals and
two
multiplexer control signals. Table
C-l
contains
a description of the outputs and inputs.
The equations for the 3-CLK DRAM State
PAL are shown
in
Figure
C-2;
those for the
2-CLK DRAM State
PAL are shown in Figure C-3. The DRAM State PAL
is
implemented
in a 16R8
PAL if the RAS signals are registered internally, or
in
a 16R6 PAL if external
registers are used. For a 16-MHz system, B-series
PAL speeds are required.
START·OF·PHASE
START·OF·PHASE
MIDDlE·OF·PHASE
MIDDlE·OF·PHASE
elK
G30107
Figure C-1.
PAL
Sampling Edges
C-1
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