Intel 80386 - Page 271

DRAM PAL DESCRIPTIONS
FUNCTION TABLE
OE CLK2 CLK CSO CSt CS2 CS3 CS4 A2 RFRQ
ROWSEL Q! QO RASO RAS! MUXOE DRAMSE[ECT A2REG
;OE
; inputs
; outputs
; I CLK2
; I I CLK ROWSEL
; I I ICSO I Q!
; I I I ICS! I I QO
; I I I I ICS2 I I I IRASO
; I I I I I CS3 I I I I IRAS!
; I I I I I I DT%R I I I I I /MUXOE
; I I I I I I I A2 I I I I I I DRAMSELECT
; I I I I I I I I RFRQ I I I I I I I A2REG
; I I I I I I I I I I I I I I I I I STATE
COMMENTS
- - - - - - - - - - - - - - - - - - - -',!, - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
LCLHXXXXXL
L C H H X X X X X L
L
C L H X X X X X L
L
C H H X X X X X L
L
C L H X X X X X L
L
C H H X X X X X L
L
C L H X X X X X L
L
C H H X X X X X L
L
C L H X X X X X L
L
C H H X X X X X L
L
C L H X X X X X L
L
C H H X X X X X L
LCLXXXXXXL
L C H X H X X X X L
L
C L X X X X X X L
L
C H X X H X X X L
L
C L X X X X X X L
LCHLLLHXLL
L C L X X X X X X L
LCHXXXLHXL
L C L X X X X X X L
LCHLLLHXXL
LCLXXXXXXL
L C H L L L H H H L
L
C L X X X X X X L
LCHXXXLLXL
L C L X X X X X X L
LCHLLLHHHL
LCLXXXXXXL
L C H H X X X X H L
L
C L X X X X X X L
LCHHXXXHXL
L C L X X X X X X L
LCHLLLHXXL
L C L X X X X X X L
LCHLLLHXHL
L C L X X X X X X L
L
C H H X X X X H H
L
C L X X X X X X H
L
C H H X X X H X H
L
C L X X X X X X H
LCHLLLHXXH
L C L X X X X X X H
L
C H L L L H X H H
L
C L X X X X X X H
L
C H H X X X X X H
L
C L X X X X X X H
L
C H H X X X X X L
LCLXXXXXXL
L C H H X X X X X L
LCLXXXXXXL
X X X X X X X X;
X,X X X X X X X;
X X X X X X X X;
X X X X X X X X;
X X X X X X X X;
X X X X X X X X;
X X X X X X X X;
X X X X X X X X;
X X X X X X X X;
X X X X X X X X;
X X X X X X X X;
HLHHHLLX;
H L H H H L L X;
HLHHHLLX;
H L H H H L L X;
H L H H H L L X;
H L H H H L L X;
HLLLHLHL;
LLLLHLLL;
LLHLHLLL;
L H H L H L L L;
L H H L H L H L;
H H L L H L H
H;
HLLHLLHH;
LLLHLLLH;
LHHHLLLH;
HHLHLLLL;
HLHHHLHX;
H L H H H L H X;
HLLHLLHH;
LLLHLLLH;
L L H H L L L H;
L H H H L L L H;
L H H H L L H H;
H H L H L L H L;
H L H H H L H
X;
H L H H H L H X;
H L L H L L H H;
L L L H L L L H;
L L H H L L L H;
L H H H L L L H;
LHHHLLHH;
H H L H L H H L;
H L H H H H H
X;
LHLHHHHX;
H L L L L H H X;
LLLLLHHX;
LHHLLHHX;
H H L L L H H X;
H L H H H H H X;
H L H H H L H X;
X initialize to IDLE
X initialize to IDLE
X initialize to IDLE
X initialize to IDLE
X initialize to IDLE
X initialize to IDLE
X initialize to IDLE
X initialize to IDLE
X initialize to IDLE
X initialize to IDLE
X initialize to IDLE
IDLE! rema in in IDLE
IDLE2 rema in in IDLE
IDLE! rem a in in IDLE
IDLE2 rema in in IDLE
IDLE! remain in IDLE
IDLE2 remain in IDLE
ACCESS! start DRAM cycle
ACCESS2 cant i nue DRAM cycle
ACCESS3 cant i nue DRAM cycle: it's write
ACCESS4 cant i nue DRAM cycle
ACCESS5 cant i nue DRAM cycle new request
ACCESS6 continue DRAM cycl e
ACCESS! start DRAM cycl e to other bank
ACCESS2 cant i nue DRAM cycle
ACCESS5 continue DRAM cycle: it's read
ACCESS6 continue DRAM cycl e
IDLE!
can't start same bank cycl e
IDLE2 wait for precharge
ACCESS! start DRAM cycle to same bank
ACCESS2 cant i nue DRAM cycle
ACCESS3 cant i nue DRAM cycl e: it's write
ACCESS4 continue DRAM cycl e
ACCESS5 cant i nue DRAM cycle new request
ACCESS6 continue DRAM cycle
IDLE! can't start same bank cycle
IDLE2 wait for precharge
ACCESS! start DRAM cycle to same bank
ACCESS2 continue DRAM cycl e
ACCESS3 cant i nue DRAM cycle: it's write
ACCESS4 continue DRAM cycl e
ACCESS5 continue DRAM cycle new request
ACCESS6 continue DRAM cycle refresh req
IDLE!
can't start: refresh pending
REFSTART2 wait for precharge
ACCESS! start refresh cycl e
ACCESS2 cant i nue refresh cycle
ACCESS5 cant i nue refresh cycle
ACCESS6 continue refresh cycle
IDLE! can't start: refresh precharge
IDLE2 wait for precharge
Figure C-3. 2-CLK DRAM State PAL Equations (Cont'd.)
C-9