Intel 80386 - Page 282

DRAM PAL DESCRIPTIONS
PAL20XIO PAL DESIGN SPECIFICATIONS
PART NUMBER: 16 MHz REFRESH INTERVAL COUNTER PAL
REFRESH INTERVAL PAL OF INTERLEAVED DRAM CONTROLLER FOR 80386 SYSTEMS
INTEL, SANTA CLARA, CALIFORNIA
CLK REFACKO REFACKI NC NC NC NC Ne NC NC NC GND
OE RFRQ NC QO Ql Q2 Q3 Q4 Q5 Q6 Q7 vce
/RFRQ := /RFRQ * Q7 * Q6 * Q5 * Q4 * Q3 * Q2 * Ql * QO ;raise at 255
+ RFRQ * /REFACKO * /REFACKI ;clear when both ACKs low
:+: /RFRQ ;else: don't change state
/QO:= /QO ;least-significant bit of counter
/QI ,-
/Q2 :=
/Q3
/Q4
:=
/Q5 ,-
/Q6
+ /Q7 * /Q6 * /Q5 * /Q4 * /Q3 ;set at 7 or less
:+: vec ;else decrement
/QI
+ /Q7 * /Q6 * /Q5 * /Q4 * /Q3
:+: /Q7 * /Q6 * /Q5 * /Q4 * /Q3
+ /QO
/Q2
+ /Q7 * /Q6 * /Q5 * /Q4 * /Q3
:+: /Q7 * /Q6 * /Q5 * /Q4 * /Q3
+ /QI * /QO
/Q3
+ /Q7 * /Q6 * /Q5 * /Q4 * /Q3
:+: /Q7 * /Q6 * /Q5 * /Q4 * /Q3
+ /Q2 * /QI * /QO
/Q4
+ /Q7 * /Q6 * /Q5 * /Q4 * /Q3
:+: /Q7 * /Q6 * /Q5 * /Q4 * /Q3
+ /Q3 * /Q2 * /QI * /QO
/Q5
+ /Q7 * /Q6 * /Q5 * /Q4 * /Q3
:+: /Q7 * /Q6 * /Q5 * /Q4 * /Q3
+ /Q4 * /Q3 * /Q2 * /Ql * /QO
/Q6
+ /Q7 * /Q6 * /Q5 * /Q4 * /Q3
:+: /Q7 * /Q6 * /Q5 * /Q4 * /Q3
+ /Q5 * /Q4 * /Q3 * /Q2 * /QI * /QO
;set at 7 or less
;set at 7 or less
;else decrement
;set at 7 or less
;set at 7 or less
; else decrement
;set at 7 or less
;set at 7 or less
;else decrement
;set at 7 or less
;set at 7 or less
; else decrement
;set at 7 or less
;set at 7 or less
;el se decrement
;set at 7 or less
;set at 7 or less
; else decrement
/Q7 '= /Q7 ;most-significant bit of counter
+ /Q7 * /Q6 * /Q5 * /Q4'* /Q3 ;set at 7 or less'
:+: /Q7 * /Q6 * /Q5 * /Q4 * /Q3 ;set at 7 or less
+ /Q6 * /Q5 * /Q4 * /Q3 * /Q2 * /Ql * /QO ;else decrement
Figure C-6_ Refresh Interval Counter PAL Equations
C-20