Intel 80386 - Page 281

DRAM PAL DESCRIPTIONS
Table C-3. Refresh Interval Counter PAL Pin Description
PAL CONTROLS
Name Connects From PAL Usage
ClK Systems ClK PAL register clock
OE Tied low
Outputs always
enabled
PAL INPUTS
Name Connects From PAL Usage Sampled
REFACKO# DRAM RASO# Indicates when refresh
Every
ClK that
REFACK1# DRAM
RAS1# starts: turns off RFRQ RFRQ is active
NCO
NC1
NC2
NC3
Not connected Not used Never
NC4
NC5
NC6
NC7
PAL OUTPUTS
Name Connects To PAL Usage Changes State
RFRQ DRAM STATE RFRQ
latch refresh request Any ClK
QO
Q1
Q2
Q3
Implements up to 9-bit
Q4
Not connected Any ClK
Q5
modulo counter
Q6
Q7
Q8
C-19