Intel 80386 - Page 289

-.
366 DRAM Control ter
~
T I H I N G
PARAMETERS
Chip Syrrbol
10 Description
From
To
Hin Max
"Hin
Max
Hin Hall. Hin Max Hin Max Hin Hall.
51C64-8 51C64-10
51C25~-12 51C256-15 2164-15 51C256-20
82384
,1
o CLK2 per i od
ClK2
I
ClK2
I
31 32 31 32 40
42
31
32 31
32
40 42
ClK2
I
ClK2
I
ClK2
I
ClK2
I
ClK2
I
ClK2
I
ClKl
I
ClK2
I
ClK2
I
ClK2
I
ClK2
I
ClK2
I
ClK2
I
ClK2
I
ClK2
I
ClK2
I
ClK2
I
ClK2
I
ClK2
I
ClK2
I
CLK2
I
CLK2
I
0
ClK2
I
ClK2
I
ClK2
I
ClK2
I
::c
ClK2
I
eLK2
I
»
82384 trciJAIT
a ClKperiod(s) rd Uai tState
ClK2
I
ClK2
I
0 0 0 0 0
0
62 64
62 64
80
84
s::
82384 twrtUAIT a CLKperiod(s) wt lJaitState ClK2
I
ClK2
I
62 64
62
64
80 84
62 64 62 64 80 84
"'C
82384
tBAK2BAK 0 ClKperiod(s) back-to-back CLK2
I
ClK2
I
62 64 62 64
160 168 124 128 124 128
160
168
»
ClK2
I
ClK2
I r-
()
386
'12
o wri te data out-delay ClK2 I 386 Date< 50
50
50
50 50 50
0
I
ClK2
I 386 Data>
m
l\J
386 * t21 o read data llet-l4l
386 Datll< ClK2
I
0 10
10 0 10 10
10 10
CII
-.J
386
,22
o read data hold
ClK2 I 366 Data>
2 999 999 2
999 999 999 999
()
366+HUX t6+tHUX
o addr fr 386 thru LatchHux
ClK2
I
rowe
3 46 46
3
46 46
46 46
::c
Cu::2
I
rowe
=c
PAL
o clock. to PAL outputs ClK2
I
Row Set \ 12 12
12 12 12
12
ClK2
I
Row Sell
-i
ClK2
I
Row Set \
5
ClK2
I
Row Sell
Z
ClK2
I
Row Set\
CII
PAlorREG Q a clock. to PAL or REG outpt CH2
I
RAS'
\
12 12
12 12
10
12
ClK2
I
RAS'
I
..
ClK2
I
RAS'
\
cu:Z
I RAS' I
cu::z
I
us#
\
Register R
a clock. to register output
CLK2
I
CASA!
I
12
12 12
12
10 12
ClK2
I
CAS'
\
ClK2
I
CAS' I
ClK2
I
CAS#
\
ClK2
I
CAS' I
ClK2
I
CAS' \
PAl-tNANO Y
o pal and wri te logic delay ClK2
I
lIE'
I
18 18
18 18
18 18
ClK2
I
UE#
\
ClK2
I
lIE,
f
Transcvr txCVR
o transc .... r prop in-to-out
rd data< 386 Data<
DrarrOata> 386 Data>
386 Data< wrt data<
386 Data> DrarrOata>
Table CoS.
DRAM Circuit Timing Parameters