Intel 80386 - Page 290

386 DRAM Controller
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TIM I N G
PARAMETERS
Chip S)1lboI 10 Description
from
To Min Max
Min Max Min Max
Min Max Hin Max Min Max
51C64-8
51C64-10
51C256-12
51C256-15
2164-15 51C256-20
DRAM tRAS I RASM pulse width
RASM
\ RAS'
80 9999 100 9999
120 9999
150 9999 150 9999 200 9999
RASM
\
RAS'
DRAM
tRC I random read/wri te cycle
RAS'
\
RAS#
140 9999
160 9999 200 9999
245 9999
260 9999
315 9999
HAS'
\
HAS'
DRAM
tRP
I RAS' precharge time
HAS'
I
.AS#
50 9999 50 9999
70 9999
85 9999 100 9999
105 9999
RAS'
I
RAS'
DRAM tCSH
CAS' hold time
HAS'
\
CASt
80 9999
100 9999 120 9999
150 9999 150 9999 200 9999
RAS'
\
CAS'
DRAM
tCAS(R)
CASM pulse width(rd cycl)
CAS'
\ CAS'
IS 9999 20 9999
25 9999
30 9999 85 9999 35 9999
OR"H
tCAS(W)
CAS' pulse width(wrt eye)
CAsM
\
CAS' 25 9999 30 9999
25 9999 30 9999 85 9999 35 9999
DRAH tllRP
wr i te to RAS' precharge
lIE'
I
RAS# -30 9999 -30 9999
10 9999
10 9999
-30 9999
10 9999
lIE,
I RAS'
e
DRAM tRUH
RAS#' to write hold time
RAS'
\
lIE,
09999 09999
15 9999 20 9999
09999 2S 9999
::0
DRAM
USR
row address set-up time
row<
RAS' 09999 09999
09999 09999
09999 09999
>
row<
RAS'
3:
DRAM tRAH row address hold time
RAS' \
colurn<
15 9999
15 9999 15 9999
20 9999 20 9999 25 9999
.AS' \
colum<
"'C
DRAM tCP
CAS' precharge
CAS' I
CAS' \
10 9999
10 9999 10 9999
10 9999 25 9999 10 9999
>
CAS' I CAS'
\
r
0
DRAM tCRP I CAS' to RASIJ precharge
CAS'
I
RAS'
\
-20 9999
-20 9999 -20 9999
-20 9999
-20 9999 -20 9999
e
I
CAS'
I
RASII
\
m
I\J
CAS'
I
RAslI
\
rJ)
(Xl
DRAM
# tRCO
RAS#' to CASII del8Y
RAS' \
CAsM
\
30 9999
30 9999
30 9999 35 9999
30 9999
40 9999
0
RAS'
\ CAS' \
::0
DRAM tASC I ealum address set-l4l
colum<
CAS.
\
09999 09999
59999
59999 09999 59999
;:;
colum< CAS#'
\
-I
DRAM tCAH
I colum address hold
CAS'
\ DrarrAddr<
10 9999
10 9999
15 9999
20 9999
25 9999 2S 9999
0
CAS'
\ DrarMddr<
DRAM tAR
I eolum addr hold fr RASII RAS# \ Dr8IMddr<
40 9999
40 9999
60
0999
70 9999 90 9999 80 9999 Z
RAS'
\ DramAddr<
rJ)
DRAM
• tON
output buffer turn 00
CAS'
\
rd data<
20 9999
20 9999
25 9999
30 9999 85 9999 35 9999
DRAM
* tOFF
output buffer turn off
CAS'
/ wrt data<
20 9999 20 9999
20 9999
25 9999 30 9999 30 9999
ORAH
* tRAC
access time from RAS'
RAS' \
rd data<
80 9999
100 9999 120 9999
150 9999 150 9999 200 9999
DRAM * tCAC
access time from CAS'
CAS'
\
rd data<
20 9999
20 9999
25 9999
30 9999 85 9999 35 9999
ORAH
* tCAA
access time fr colllTfl adr colt.rrn< rd data< 45 9999
55 9999
55 9999
70 9999 85 9999
90 9999
DRAM
IRSH(')
RAS# hold time (rd cycle)
CAS'
\
RAS'
I
10 9999
10 9999
10 9999 10 9999 85 9999
10 9999
DRAM
tRCS
read coornand set-up time
RAS' \
rd datB<
09999 09999
09999
09999 09999 09999
DRAM tCAR
colLllYl address to RAS#'
colurn< RAS#
I
45 9999
55
9999
55 9999 70 9999 85 9999 90 9999
DRAM
tRCH
read com hold ref to CAS# CAStI
I
WE#
\
09999 09999
09999
09999
5 9999 09999
DRAM
tRRH
read com hold ref to RAS#
.AS#
I
WE#
\
10 9999
10 9999
10 9999 10 9999 20 9999
10 9999
DRAM
tRSH(IJ)
RAS# hold time (wrt cycl)
C",slt
\
RAS#
I
35 9999
35 9999 25 9999
30 9999 85 9999 35 9999
DRAM
tRUL
wr i te coomand to RASII
WE'
\
RASIt
I
25 9999 30 9999
25 9999
30 9999 40 9999 35 9999
DRAM tC\oIL
write coomand to CAS'
WE'
\
CASt
I
25 9999
30 9999 25 9999
30 9999 40 9999
35 9999
DRAM
tUP
write conmand pulse width
WE'
\
WE'
I
20
9999 20 9999
20 9999
25 9999 30 9999 30 9999
DRAM tYCS
write conmand set-up time
WE'
\
CAS#
\
09999 09999
09999 09999
10 9999
09999
ORAH tYCH
write cQITfTland hold time
CAS' \
WEN
I
25 9999 30 9999
25 9999
30 9999 30 9999 35 9999
DRAM tOS
data- in set-up time
wrt data<
CAS#
\
09999
o 9999
o 9999
09999
09999
09999
DRAM tOH
data- in hold time
CAS It \ Dranilata> 20 9999
20 9999
20
9999 25 9999 3D 9999
30 9999
Table CoS.
DRAM Circuit Timing Parameters (Cont'd.)