Intel 80386 - Page 291

386 DRAH Controller
I
Ii
T I H I N G
CALCULAT
o N 5
Chip
Syrrbol
10 Description
From
To Min
Hax Min Max
Min Max Min Max Min Max
Min Max
51C64-8
51C64-10
51C256-12 51C256-15 2164-15 51C256-20
DR""
tRAS
RAS# pulse width
80 9999 100 9999
120 9999 150 9999 150 9999 200 9999
'0
... trd.JAI T ... t 1 +,1
+,1
+,1
-0
'AS'
\
'AS'
112 140 112
140 148
180 174 204 180 198 228 264
'0
... twrtIJAIT ... t1 +,1
+,1
+,1
-g
'A5I \ RAS'
174
204 174 204
228 264 174 204 180 198 228 264
DR""
IRC
random read/write cycle
140 9999 160 9999
200 9999
245 9999 260 9999 315 9999
+0
... tBAK2BAK ... trcA.lAIT H1 +,1
+11
+11
-Q
'AS'
\
'AS'
\
174
204
174 204 308 348
298 332 304 326 188 432
.Q
... tBAK2BAK ... twrtIJAI T+t 1 +,1
+,1
+,1
-Q
us.
\
'AS'
\
236
268
236 268
188 432 298 332 304 326 188 432
oRAH
IRP
RAS' precharge time
50 9999
50 9999
70 9999
85 9999
100 9999
105 9999
I I
0
:0
'0
... tBAK2BAK-g
'AS'
'AS'
50 76
50 76 148
180
112
140
118 134 148 180
>
+Q
... tBAK2BA;:::-g
RAS'
RAS'
50 76 50
76 148 180 112 140 118
134
148 180
3:
"tI
DR""
tCSH
CAS' hold ti...e
80 9999 100 9999
120 9999
150 9999 150 9999
200 9999
>
+,
... trct.JAIT ... t1
+,1
+,1 +,1
-Q
r
()
'AS'
\
CAS'
112 140 112
140 148
180
174
204
180
198
228
264
0
I
.,
HwrtIJAIT ... t1
+,1
+,1 +,1
-Q
m I\:)
'AS'
\
CAS'
174
204 174
204 228 264 174 204 180 198 228 264
CJ)
(!)
()
CAS' pulse width(rd eyel)
35 9999
:0
DRAM
'CAS(')
15 9999
20 9999
25 9999 30 9999 85 9999
i5
'R
... trcA.lAIT ... t1
+,1
-,
CAS' \ CAS'
50
76 50 76
68
96 112 140 118 134 148
180
-t
ORAH
tCAS(IJ)
CAS' pulse width(wrt eye)
25 9999
30 9999
25 9999 30 9999 85 9999 35 9999
I
I~
.R
... twrtI.lAIT ... t1
-,
CAS' \
CAS'
81
108 81 108
108
.138 81 108 87 102 108 138
DRAM tl.lRP wr i te to RAS' preeharge
-30 9999
-30 9999
10 9999 10 9999
-30 9999
10 9999
.0 +,1 -~
~E'
RAS#
13
42
13 42
22 52 13 42 17 40 22 52
+0
... tBAK2BAK ... twrtI.lAI T - t 1
-~
~E'
RAS'
74 107
74 107 180
222 136 171 140 169 180 222
DRAM tRIJH
RAStt to write hold time
09999
09999
15 9999 20 9999 09999 25 9999
+"
+,1
+,1
-0
RAS'
lIE'
52
82
52 82
70 102 52 82 54 78 70 102
DRAM tASR
row address set-up time
09999
o 9999
09999 09999 09999 09999
.0 +,1
·,1
-t6+tHU)(
row<
RAS#
16 13
16 13 34 93
16 13 20 71 34 93
.a -ttBAK2BAK ... trd.lAIT -t6HHU)( row<
RAS'
16 13 16
13 114 177 140 201
144 199 194 261
DRAM
tRAH row address hold time
15 9999
15 9999 15 9999
20 9999 20 9999 25 9999
+tHUX
.p .,1
-0
RAS#
colurn<
23 55
23 55
32 65 23 55 25 51 32 65
+tHUX
'P
.,1
-0
RAS# colurn<
23 5S 23
SS 32 6S 23 55
25 51 32 6S
Table C-S.
DRAM Circuit Timing Parameters (Cont'd.)