Intel 80386 - Page 292

_.
366 DRAM Controller
I
Ie[:
T J H J N G
CALCULATIONS
Chip SynboJ
10 Description
From To Min Max Min Max Hin Max
Min Max
Hin Max
Hin Max
51C64-8 51C64-10 51C256-12
51C256-15
2164-15
51C256-20
DRAM
,CP
CAS. precharge
10 9999
10 9999
10 9999 10 9999
25 9999
10 9999
+R
+t1
+tl +tl
.. tBAIC28AK-R
CAS.
CAS'
143 In 143 In
268 306 205
236 211
230
268 306
+R
+t1 +t1
... tBAK2BAIC·R
CAS'
CAS'
112 140 112
140 228 264 114
204 180
198
228
264
aRAM lCRP
CAS' to RAS' precharge -20 9999 -209999 -20 9999
-20 9999
-20 9999 -20 9999
+0 -R
CAS.
lAS'
-12
12
-12
12
-12
12
-12
12
-6
6
-12 12
+0 +tSAK28AIC-R
CAS' RAS'
50 76 50 76
148
180 112
140 118 134 148
180
+0 +tBAKlBAK-R
CAS'
RAS'
50 76 50 76
148 180 112
140 118 134
148 180
DRAM
• ,Rca
RAS' '0 CAS' delay 30 9999 309999 30 9999
35 9999
30 9999 40 9999
'R
+t1
+',
-Q
RAS'
CAS'
~O 76 50 76
68 96 50 76
56 70 68
96
+R
+',
+',
+',
-Q
RAS'
CAS'
81 108
81
108 108 138
81 108
87 102 108 138
C
:u
aRAM usc colum address set-up 09999
09999 09999
59999
59999
59999
>
+R +t1
-p
-tI«JX
colum<
CAS'
8
40
8
40 17 50 8
40
12 38 17
50
:s:
'R
+', +',
-p
-tMUX
col\ll'll<
CAS'
39
n 39 n
57 92
39 n
43 70 57 92
'tI
>
DRAM tCAH
colum address hold
10 9999 10 9999 15 9999
20 9999
25 9999 25 9999
I
I~
()
.. tHUX
.p
+t1
+',
+t1 -R
J
CAS'
\ DramAddr< 85 119 85 119
112
149 85 119
87
115
112 149
CJJ
0
.. tNUX
+p
+t1 +t1 -R
CAS'
\ DramAddr< 54 87 54 87 n
107 54
87 56 83
72 107
()
:u
aRAM tAR
colutl"l addr hold fr RAS.
40 9999 40 9999 60 9999
70 9999
90 9999 80 9999
=a
.. tNUX
.p
+tl
+',
+t1
+',
+t1
-Q
-I
lAS'
\ Or~ddr< 147 183 147 183
192
233 147 183
149 179
192 233
(5
.. tHUX
+p
+t1
+',
+t1
+t1
+',
-Q
RAS'
\ DramAddr< 147
183 147 183
192
233 141 183
149
179 192 233
Z
C/l
DRAM
.. tON
output buffer turn on
20 9999 20 9999
25 9999 30 9999
85 9999
35 9999
• txCVR
-,21 +crcAJAIT +tl +t1
-R
CAS.
\
rd data< 33 62 40 64
51 82 95
126 97 122
131 166
DRAM
• tOFF
output buffer turn off 20 9999 20 9999 20 9999
25 9999
30 9999
30 9999
+tXC'IIi
+t12
+',
+tBAK28AK-R
CAS. I Nrc data< 84 153 82 146
191 261 146 211
148 213 191
261
DRAM
.. tRAC access time from RAS# 80 9999 100 9999 120 9999
150 9999
150 9999 200 9999
-txCVR
-,21 +trdWAIT +t1
+', +',
+tl
-0
RAS' \
rd data< 95 126 102 128 131
166 151
190 159 186 211
250
ORAH
.. tCAe access time from CAS# 20 9999 20 9999 25 9999
30 9999 85 9999
35 9999
. (XCIIR -,21 +trdUAIT +t1
+',
-R
CAS#
\
rd data<
33
62
40
64
51 82
95 126 91 122
131 166
Table C-S.
DRAM
Circuit Timing Parameters (Cont'd.)