Intel 80386 - Page 293

_.
386 DRAM Controller
l
1 MIN G
CALCULAT 1 OMS
I .
Chip
Sl"i>ol 10 Description
fran
To Min Max
Min Max Min Max Min Max
Min Max Min Max
51C64-8
51C64-10 51C256-12
51C256-15 2164-15 51C256-20
ORA"
• ,eM
access t ilne fr colLlln edr
45 9999 55 9999
55 9999
70 9999 85 9999 90 9999
- <xCVR
-'21
+trcllAIT +11
+'1
+'1
-p
-'NUX
colurn<
rd datae
53 90 60 92
80 -120
115 154 115 154 160 204
DRAM
'RSH(R)
RAS'
hold 'ime (rd cycle)
109999
10 9999 10 9999 109999 85 9999 109999
+0
+trdJAn +t1 +,1
-R
CAS'
\ HAst
50 76 50 76 68 96 112 140 118 134 148 180
DRAM ,RCS
read cClllRllrd set·. ti ..
09999
09999 09999 09999 09999 09999
-tXCW
-,21
+trd.lAIT +t1 +,1
+t1
+t1
-Q
HAS' \
rd datl<
95
126 102 128 131 166 157 190 159 186 211 250
DRAM
'CAR
cohlln address to RAS'
45 9999 55 9999
55 9999 70 9999 85 9999
90 9999
I
I~
+0
+trc:llAIT +t1
+'1
+t1
-p
- tIIJX
coll.lln< HAst 70 104 70
104
97 134 132 168 136
166 177 218
'tI
DRAM
IRCH
read COllI hold ref to CAS.
09999 09999
09999 09999 59999 09999
>
+W +,1
+,1
+'BAK2BAK-R
CAst
WE'
114 146
114 146
230 270 176 210 178 206 230
270
r-
0
C
I
m
~
DRAM
tRRH
read COlD hold ref to RAS'
109999
10 9999
109999 109999 20 9999
10 9999
en
+W
+'1
+'1
+tBAK28AK -Q
HAst
WE'
114 146
114 146
230 270
176 210
178 206 230 270
0
:D
DRAM tRSH(W)
RAS' hold 'ime (wr' eyell 35 9999 35 9999
25
9999 309999 85 9999 35 9999
;;
-I
+0
+twrUIAIT+tl -R
CAS'
\ RAS'
81 108 81 108 108 138 81
108 87
102 108 138
0
Z
DRAM ,RWL
write ccxrmand to RAS' 25 9999 30 9999
25
9<>99
309999 409999
35 9999
en
+0
+tvrtWAIT+t1
+,1
-W
WE'
\ HAS'
106
138 106
138 142
178 106 138 110 136 142
178
ORAM
'CWL
uri te camnand to CAS'
25
9999 30 9999
25 9999 309999 40 9999 35 9999
+R
+twrtVAIT+tl
+'1
-W
WE'
\
CAS'
106
138 106 138 142
178
106 138 110 136
142 178
DRAM
'WP
write conmand pulse width 20 9999
209999
209999 25 9999 30 9999
30 9999
+W
+,1
+'1
+,1
-W
WE'
lIE'
77
112 77112 104
142
77 112 77 112 104 142
DRAM ttolCS
wri Ie comnand set·up time
09999 09999 09999
09999 -109999
09999
+R
+tl
-W
lIE'
\ CAS'
13 42 13
42
22 52 13 42 17 40
22 52
DRAM
,WCH
write corrmand hold time
25 9999
30 9999 25 9999 309999 30 9999 35 9999
'W
+,1
+,1
-R
CAS'
lIE'
i
52 82 52
82
70 102 52 82 54 78 70 102
Table C-S.
DRAM Circuit Timing Parameters (Cont'd.)