Intel 80386 - Page 294

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386 DRAM Controller
T I H I N G CALCULATIONS
10 Description from
To Min Max Min Max
Min Max
Min Max
51C64-8
51C64-10 51C256-12 51C256-15
data- in set-up time
09999 09999
09999
09999
+',
-112
'UCVR wrt daU<
CAS'
5 73 12 75 23 93 5 73
data-
in hold time
20 9999 20 9999 20 9999 25 9999
+',
+twrU'AIT+t1
-R
CAS'
\ DrllillOata> 115 185 113 178
151 225
115 185
Table CoS. DRAM Circuit Timing Parameters (Cont'd.)
Min Max
2164-15
09999
9 71
30 9999
117 181
Min Max
51C256-20
09999
23
93
30 9999
151 225
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