Errata
Specification Update 17
AA3. Data Breakpoints on the High Half of a Floating Point Line Split May
Not Be Captured
Problem: When a floating point load which splits a 64-byte cache line gets a floating
point stack fault, and a data breakpoint register maps to the high line of the
floating point load, internal boundary conditions exist that may prevent the
data breakpoint from being captured.
Implication: When this erratum occurs, a data breakpoint will not be captured.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AA4. MOV CR3 Performs Incorrect Reserved Bit Checking When in PAE
Paging
Problem: The MOV CR3 instruction should perform reserved bit checking on the upper
unimplemented address bits. This checking range should match the address
width reported by CPUID instruction 0x8000008. This erratum applies
whenever PAE is enabled.
Implication: Software that sets the upper address bits on a MOV CR3 instruction and
expects a fault may fail. This erratum has not been observed with
commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AA5. VMEntry from 64-bit Host to 32-bit Guest may Cause IERR# with
Hyper-Threading Technology Enabled
Problem: When transitioning from a 64-bit host environment to a 32-bit guest
environment via a VMEntry, internal conditions in a processor with Hyper-
Threading enabled may cause a speculative page-table walk to be
prematurely terminated, resulting in a processor hang and the assertion of
IERR#.
Implication: An IERR# may occur on VMEntry from a 64-bit to a 32-bit environment with
Hyper-Threading enabled.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
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