Intel Cyclone 10 GX FPGA - Page 48

Figure 15. The XCVR Tab
Status
Displays the following status information during a loopback test:
• PLL lock: Shows the PLL locked or unlocked state.
• Pattern sync: Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected.
• Details: Shows the PLL lock, pattern sync status and number of errors for a single
channel.
Port
Allows you to specify which interface to test. The following port tests are available:
5 Board Test System
UG-20105 | 2017.12.18
Intel
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10 GX FPGA Development Kit User Guide
48