Intel Cyclone 10 GX FPGA - Page 5

• User-defined reference clock input from FMC card
— 1 for FMC transceiver to FPGA transceiver
— 2 for FMC LA reference to FPGA core
— 2 for FMC clock reference to FPGA core
• One external differential input through SMA, AC coupled
• One single-ended LVCMOS clock output through SMA, DC coupled
Transceiver Interfaces
• 12 transceivers organized in two banks
• 4 channels for PCIe x4 Gen2
• 2 channels for 2 SFP+ supporting 10 GE
• 1 channel for USB3.1 SuperSpeed
• 5 channels for FMC card
Memory Interfaces
• 1 channel of x40 DDR3 @ 933 MHz
Communication Ports
• 10/100/1000Base-T Ethernet port with SGMII (LVDS)
• USB3.1 Type-C supporting SuperSpeed, backward compatible with USB2.0
• 2 SFP+ supporting 10GE
• FMC expansion card:
— 12G SDI: Semtech RDK-12GSRD-ALTRA00 Evaluation Board
— 8G DisplayPort: Bitec FMC DisplayPort Daughter Card
— 6G HDMI 2.0: Bitec FMC HDMI Daughter Card
Pushbuttons
• 3 User Push Buttons
• 1 User Program selecting Pushbutton
• 1 nCONFIG Pushbutton to initiate configuration
• 1 FPGA reset Pushbutton to reset the FPGA logic
Switches
• 4 User DIP Switches
• DIP switch for MSEL
• DIP switch for JTAG chain selection
• DIP switch for clock source selection
1 Overview
UG-20105 | 2017.12.18
Intel
®
Cyclone
®
10 GX FPGA Development Kit User Guide
5