Intel Cyclone 10 GX FPGA - Page 59

Note:
Currently, only OUT0 and OUT1 can support fractional synthesis output for this board.
If you want to change the divider setting, you should use Silicon Laboratories'
ClockBuilder tool to generate the register map and use import function on this
application.
The controls of the clock controller are described below:
F_vco
Displays the generating signal value of the voltage-controlled oscillator.
Frequency
Allows you to specify the frequency of the clock MHz.
Divider
Display the divider mode and value currently being used on this board.
Disable
Allows you to disable a single output.
Read
Reads the current frequency setting for the oscillator.
Set
Sets the programmable oscillator frequency for the selected clock to the value in
OUT0, OUT1, OUT4, OUT6 and OUT7 controls for the Si5332. Frequency changes might
take several milliseconds to take effect. You might see glitches on the clock during this
period. Intel recommends resetting the FPGA logic after changing frequencies.
Import
Import register map file generated from Silicon Laboratories ClockBuilder Desktop.
5 Board Test System
UG-20105 | 2017.12.18
Intel
®
Cyclone
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10 GX FPGA Development Kit User Guide
59