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Specification Update
AAU84. The PECI Bus May Be Tri-stated after System Reset
Problem: During power-up, the processor may improperly assert the PECI (Platform Environment
Control Interface) pin. This condition is cleared as soon as Bus Clock starts toggling.
However, if the PECI host (also referred to as the master or originator) incorrectly
determines this asserted state as another PECI host initiating a transaction, it may
release control of the bus resulting in a permanent tri-state condition.
Implication: Due to this erratum, the PECI host may incorrectly determine that it is not the bus
master and consequently PECI commands initiated by the PECI software layer may
receive incorrect/invalid responses.
Workaround: To workaround this erratum the PECI host should pull the PECI bus low to initiate a
PECI transaction.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU85. The Combination of a Page-Split Lock Access And Data Accesses That
Are Split Across Cacheline Boundaries May Lead to Processor Livelock
Problem: Under certain complex micro-architectural conditions, the simultaneous occurrence of a
page-split lock and several data accesses that are split across cacheline boundaries
may lead to processor livelock.
Implication: Due to this erratum, a livelock may occur that can only be terminated by a processor
reset. Intel has not observed this erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU86. Processor Hangs on Package C6 State Exit
Problem: An internal timing condition in the processor power management logic will result in
processor hangs upon a Package C6 state exit.
Implication: Due to this erratum, the processor will hang during Package C6 state exit.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU87. A Synchronous SMI May be Delayed
Problem: A synchronous SMI (System Management Interrupt) occurs as a result of an SMI
generating I/O Write instruction and should be handled prior to the next instruction
executing. Due to this erratum, the processor may not observe the synchronous SMI
prior to execution of the next instruction.
Implication: Due to this erratum, instructions after the I/O Write instruction, which triggered the
SMI, may be allowed to execute before the SMI handler. Delayed delivery of the SMI
may make it difficult for an SMI Handler to determine the source of the SMI. Software
that relies on the IO_SMI bit in SMM save state or synchronous SMI behavior may not
function as expected.
Workaround: A BIOS code change has been identified and may be implemented as a workaround for
this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
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