45
Specification Update
Implication: This erratum may result in unexpected behavior of software that uses x87 FPU
instructions.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: None identified.
AAU96. Under Certain Low Temperature Conditions, Some Uncore
Performance Monitoring Events May Report Incorrect Results
Problem: Due to this erratum, under certain low operating temperatures, a small number of Last
Level Cache and external bus performance monitoring events in the uncore report
incorrect counts. This erratum may affect event codes in the ranges 00H to 0CH and
40H to 43H.
Implication: Due to this erratum, the count value for some uncore Performance Monitoring Events
may be inaccurate. The degree of under or over counting is dependent on the
occurrences of the erratum condition while the counter is active. Intel has not
observedthis erratum with any commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU97. CKE May go Low Within tRFC(min) After a PD Exit
Problem: After a refresh command is issued, followed by an early PD(Power Down) Entry and
Exit, the CKE (Clock Enable) signal may be asserted low prior to tRFC(min), the
Minimum Refresh Cycle timing. This additional instance of CKE being low causes the
processor not to meet the JEDEC DDR3 DRAM specification requirement (Section
4.17.4 Power-Down clarifications - Case 3).
Implication: Due to this erratum, the processor may not meet the JEDEC DDR3 DRAM specification
requirement that states: “CKE cannot be registered low twice within a tRFC(min)
window”. Intel has not observed any functional failure due to this erratum.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU98. Erratum AAU98 added to this specification Update in error; all erratum
details removed from the specification update document.
AAU99. Performance Monitor Events for Hardware Prefetches Which Miss The
L1 Data Cache May be Over-Counted
Problem: Hardware prefetches that miss the L1 data cache but cannot be processed immediately
due to resource conflicts will count and then retry. This may lead to incorrectly
incrementing the L1D_PREFETCH.MISS (event 4EH, umask 02H) event multiple times
for a single miss.
Implication: The count reported by the L1D_PREFETCH.MISS event may be higher than expected.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAU100. VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
Problem: If the “load IA32_PERF_GLOBAL_CTRL” VM-exit control is 1, a VM exit should load the
IA32_PERF_GLOBAL_CTRL MSR (38FH) from the IA32_PERF_GLOBAL_CTRL field in the
guest-state area of the VMCS. Due to this erratum, such a VM exit may instead clear
bits 34:32 of the MSR, loading only bits 31:0 from the VMCS.
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