Errata
28
Specification Update
AAZ43. Performance Monitor Counters May Count Incorrectly
Problem: Under certain circumstances, a general purpose performance counter, IA32_PMC0-4
(C1H - C4H), may count at core frequency or not count at all instead of counting the
programmed event.
Implication: The Performance Monitor Counter IA32_PMCx may not properly count the programmed
event. Due to the requirements of the workaround there may be an interruption in the
counting of a previously programmed event during the programming of a new event.
Workaround:Before programming the performance event select registers, IA32_PERFEVTSELx MSR
(186H - 189H), the internal monitoring hardware must be cleared. This is accomplished
by first disabling, saving valid events and clearing from the select registers, then
programming three event values 0x4300D2, 0x4300B1 and 0x4300B5 into the
IA32_PERFEVTSELx MSRs, and finally continuing with new event programming and
restoring previous programming if necessary. Each performance counter, IA32_PMCx,
must have its corresponding IA32_PREFEVTSELx MSR programmed with at least one of
the event values and must be enabled in IA32_PERF_GLOBAL_CTRL MSR (38FH) bits
[3:0]. All three values must be written to either the same or different
IA32_PERFEVTSELx MSRs before programming the performance counters. Note that
the performance counter will not increment when its IA32_PERFEVTSELx MSR has a
value of 0x4300D2, 0x4300B1 or 0x4300B5 because those values have a zero UMASK
field (bits [15:8]).
Status: For the steppings affected, see the Summary Tables of Changes.
AAZ44. Performance Monitor Event Offcore_response_0 (B7H) Does Not
Count NT Stores to Local DRAM Correctly
Problem: When a IA32_PERFEVTSELx MSR is programmed to count the Offcore_response_0
event (Event:B7H), selections in the OFFCORE_RSP_0 MSR (1A6H) determine what is
counted. The following two selections do not provide accurate counts when counting NT
(Non-Temporal) Stores:
• OFFCORE_RSP_0 MSR bit [14] is set to 1 (LOCAL_DRAM) and bit [7] is set to 1
(OTHER): NT Stores to Local DRAM are not counted when they should have been.
• OFFCORE_RSP_0 MSR bit [9] is set to (OTHER_CORE_HIT_SNOOP) and bit [7] is
set to 1 (OTHER): NT Stores to Local DRAM are counted when they should not have
been.
Implication: The counter for the Offcore_response_0 event may be incorrect for NT stores.
Workaround:None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
AAZ45. EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits
after a Translation Change
Problem: This erratum is regarding the case where paging structures are modified to change a
linear address from writable to non-writable without software performing an
appropriate TLB invalidation. When a subsequent access to that address by a specific
instruction (ADD, AND, BTC, BTR, BTS, CMPXCHG, DEC, INC, NEG, NOT, OR, ROL/ROR,
SAL/SAR/SHL/SHR, SHLD, SHRD, SUB, XOR, and XADD) causes a page fault or an EPT-
induced VM exit, the value saved for EFLAGS may incorrectly contain the arithmetic flag
values that the EFLAGS register would have held had the instruction completed without
fault or VM exit. For page faults, this can occur even if the fault causes a VM exit or if
its delivery causes a nested fault.
Implication: None identified. Although the EFLAGS value saved by an affected event (a page fault or
an EPT-induced VM exit) may contain incorrect arithmetic flag values, Intel has not
identified software that is affected by this erratum. This erratum will have no further
effects once the original instruction is restarted because the instruction will produce the
same results as if it had initially completed without fault or VM exit.
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